diff options
| -rw-r--r-- | doc/README.fsl-esdhc | 5 | ||||
| -rw-r--r-- | include/fsl_esdhc.h | 14 |
2 files changed, 18 insertions, 1 deletions
diff --git a/doc/README.fsl-esdhc b/doc/README.fsl-esdhc new file mode 100644 index 0000000000..b70f271d1a --- /dev/null +++ b/doc/README.fsl-esdhc @@ -0,0 +1,5 @@ +CONFIG_SYS_FSL_ESDHC_LE means ESDHC IP is in little-endian mode. +CONFIG_SYS_FSL_ESDHC_BE means ESDHC IP is in big-endian mode. + +Accessing ESDHC registers can be determined by ESDHC IP's endian +mode or processor's endian mode. diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index 9814964937..c1b6648591 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -162,7 +162,19 @@ struct fsl_esdhc_cfg { }; /* Select the correct accessors depending on endianess */ -#if __BYTE_ORDER == __LITTLE_ENDIAN +#if defined CONFIG_SYS_FSL_ESDHC_LE +#define esdhc_read32 in_le32 +#define esdhc_write32 out_le32 +#define esdhc_clrsetbits32 clrsetbits_le32 +#define esdhc_clrbits32 clrbits_le32 +#define esdhc_setbits32 setbits_le32 +#elif defined(CONFIG_SYS_FSL_ESDHC_BE) +#define esdhc_read32 in_be32 +#define esdhc_write32 out_be32 +#define esdhc_clrsetbits32 clrsetbits_be32 +#define esdhc_clrbits32 clrbits_be32 +#define esdhc_setbits32 setbits_be32 +#elif __BYTE_ORDER == __LITTLE_ENDIAN #define esdhc_read32 in_le32 #define esdhc_write32 out_le32 #define esdhc_clrsetbits32 clrsetbits_le32 |
