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-rw-r--r--board/altera/socfpga/socfpga_cyclone5.c16
1 files changed, 16 insertions, 0 deletions
diff --git a/board/altera/socfpga/socfpga_cyclone5.c b/board/altera/socfpga/socfpga_cyclone5.c
index ce625e54d0..772a58ed9e 100644
--- a/board/altera/socfpga/socfpga_cyclone5.c
+++ b/board/altera/socfpga/socfpga_cyclone5.c
@@ -12,7 +12,9 @@
#include <usb/s3c_udc.h>
#include <usb_mass_storage.h>
+#include <micrel.h>
#include <netdev.h>
+#include <phy.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -44,6 +46,20 @@ int board_init(void)
return 0;
}
+int board_phy_config(struct phy_device *phydev)
+{
+ /*
+ * These skew settings for the KSZ9021 ethernet phy is required for ethernet
+ * to work reliably on most flavors of cyclone5 boards.
+ */
+ ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
+ 0x0);
+ ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
+ 0x0);
+ ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
+ 0xf0f0);
+}
+
#ifdef CONFIG_USB_GADGET
struct s3c_plat_otg_data socfpga_otg_data = {
.regs_otg = CONFIG_USB_DWC2_REG_ADDR,
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