diff options
27 files changed, 1962 insertions, 318 deletions
diff --git a/arch/arm/cpu/armv8/zynqmp/Kconfig b/arch/arm/cpu/armv8/zynqmp/Kconfig index 9a19dfa77f..6c71d7840e 100644 --- a/arch/arm/cpu/armv8/zynqmp/Kconfig +++ b/arch/arm/cpu/armv8/zynqmp/Kconfig @@ -1,13 +1,5 @@ if ARCH_ZYNQMP -choice - prompt "Xilinx ZynqMP board select" - -config TARGET_ZYNQMP_EP - bool "ZynqMP EP Board" - -endchoice - config SYS_BOARD default "zynqmp" @@ -18,7 +10,12 @@ config SYS_SOC default "zynqmp" config SYS_CONFIG_NAME - default "xilinx_zynqmp_ep" if TARGET_ZYNQMP_EP + string "Board configuration name" + default "xilinx_zynqmp" + help + This option contains information about board configuration name. + Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header + will be used for board configuration. config ZYNQMP_USB bool "Configure ZynqMP USB" diff --git a/arch/arm/mach-zynq/include/mach/sys_proto.h b/arch/arm/mach-zynq/include/mach/sys_proto.h index 882beabe13..44c9b50fe5 100644 --- a/arch/arm/mach-zynq/include/mach/sys_proto.h +++ b/arch/arm/mach-zynq/include/mach/sys_proto.h @@ -19,6 +19,8 @@ extern int zynq_slcr_get_mio_pin_status(const char *periph); extern void zynq_ddrc_init(void); extern unsigned int zynq_get_silicon_version(void); +int zynq_board_read_rom_ethaddr(unsigned char *ethaddr); + /* Driver extern functions */ extern void ps7_init(void); diff --git a/arch/microblaze/cpu/interrupts.c b/arch/microblaze/cpu/interrupts.c index b6d6610f2f..010ca4a02c 100644 --- a/arch/microblaze/cpu/interrupts.c +++ b/arch/microblaze/cpu/interrupts.c @@ -10,10 +10,13 @@ #include <common.h> #include <command.h> +#include <fdtdec.h> #include <malloc.h> #include <asm/microblaze_intc.h> #include <asm/asm.h> +DECLARE_GLOBAL_DATA_PTR; + void enable_interrupts(void) { debug("Enable interrupts for the whole CPU\n"); @@ -112,11 +115,26 @@ static void intc_init(void) int interrupt_init(void) { int i; + const void *blob = gd->fdt_blob; + int node = 0; + + debug("INTC: Initialization\n"); + + node = fdt_node_offset_by_compatible(blob, node, + "xlnx,xps-intc-1.00.a"); + if (node != -1) { + fdt_addr_t base = fdtdec_get_addr(blob, node, "reg"); + if (base == FDT_ADDR_T_NONE) + return -1; + + debug("INTC: Base addr %lx\n", base); + intc = (microblaze_intc_t *)base; + irq_no = fdtdec_get_int(blob, node, "xlnx,num-intr-inputs", 0); + debug("INTC: IRQ NO %x\n", irq_no); + } else { + return node; + } -#if defined(CONFIG_SYS_INTC_0_ADDR) && defined(CONFIG_SYS_INTC_0_NUM) - intc = (microblaze_intc_t *)CONFIG_SYS_INTC_0_ADDR; - irq_no = CONFIG_SYS_INTC_0_NUM; -#endif if (irq_no) { vecs = calloc(1, sizeof(struct irq_action) * irq_no); if (vecs == NULL) { diff --git a/arch/microblaze/cpu/timer.c b/arch/microblaze/cpu/timer.c index 3960bbb08a..8845e07d0e 100644 --- a/arch/microblaze/cpu/timer.c +++ b/arch/microblaze/cpu/timer.c @@ -7,9 +7,12 @@ */ #include <common.h> +#include <fdtdec.h> #include <asm/microblaze_timer.h> #include <asm/microblaze_intc.h> +DECLARE_GLOBAL_DATA_PTR; + volatile int timestamp = 0; microblaze_timer_t *tmr; @@ -28,9 +31,6 @@ void __udelay(unsigned long usec) i = get_timer(0); while ((get_timer(0) - i) < (usec / 1000)) ; - } else { - for (i = 0; i < (usec * XILINX_CLOCK_FREQ / 10000000); i++) - ; } } @@ -46,12 +46,35 @@ int timer_init (void) int irq = -1; u32 preload = 0; u32 ret = 0; + const void *blob = gd->fdt_blob; + int node = 0; + u32 cell[2]; -#if defined(CONFIG_SYS_TIMER_0_ADDR) && defined(CONFIG_SYS_INTC_0_NUM) - preload = XILINX_CLOCK_FREQ / CONFIG_SYS_HZ; - irq = CONFIG_SYS_TIMER_0_IRQ; - tmr = (microblaze_timer_t *) (CONFIG_SYS_TIMER_0_ADDR); -#endif + debug("TIMER: Initialization\n"); + + node = fdt_node_offset_by_compatible(blob, node, + "xlnx,xps-timer-1.00.a"); + if (node != -1) { + fdt_addr_t base = fdtdec_get_addr(blob, node, "reg"); + if (base == FDT_ADDR_T_NONE) + return -1; + + debug("TIMER: Base addr %lx\n", base); + tmr = (microblaze_timer_t *)base; + + ret = fdtdec_get_int_array(blob, node, "interrupts", + cell, ARRAY_SIZE(cell)); + if (ret) + return ret; + + irq = cell[0]; + debug("TIMER: IRQ %x\n", irq); + + preload = fdtdec_get_int(blob, node, "clock-frequency", 0); + preload /= CONFIG_SYS_HZ; + } else { + return node; + } if (tmr && preload && irq >= 0) { tmr->loadreg = preload; diff --git a/board/xilinx/microblaze-generic/xparameters.h b/board/xilinx/microblaze-generic/xparameters.h index ccb528ed92..dc5645bd14 100644 --- a/board/xilinx/microblaze-generic/xparameters.h +++ b/board/xilinx/microblaze-generic/xparameters.h @@ -13,21 +13,10 @@ #define XILINX_BOARD_NAME microblaze-generic -/* System Clock Frequency */ -#define XILINX_CLOCK_FREQ 100000000 - /* Microblaze is microblaze_0 */ #define XILINX_USE_MSR_INSTR 1 #define XILINX_FSL_NUMBER 3 -/* Interrupt controller is opb_intc_0 */ -#define XILINX_INTC_BASEADDR 0x41200000 -#define XILINX_INTC_NUM_INTR_INPUTS 6 - -/* Timer pheriphery is opb_timer_1 */ -#define XILINX_TIMER_BASEADDR 0x41c00000 -#define XILINX_TIMER_IRQ 0 - /* GPIO is LEDs_4Bit*/ #define XILINX_GPIO_BASEADDR 0x40000000 diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index 2f17e977a4..4c20450b63 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -98,6 +98,19 @@ int checkboard(void) } #endif +int zynq_board_read_rom_ethaddr(unsigned char *ethaddr) +{ +#if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \ + defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) + if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR, + CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET, + ethaddr, 6)) + printf("I2C EEPROM MAC address read failed\n"); +#endif + + return 0; +} + int dram_init(void) { int node; diff --git a/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.c b/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.c index 2c0fecac43..83daf7bf15 100644 --- a/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.c +++ b/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.c @@ -310,11 +310,11 @@ unsigned long ps7_clock_init_data_3_0[] = { /* .. SRCSEL = 0x0 */ /* .. ==> 0XF8000154[5:4] = 0x00000000U */ /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */ - /* .. DIVISOR = 0x14 */ - /* .. ==> 0XF8000154[13:8] = 0x00000014U */ - /* .. ==> MASK : 0x00003F00U VAL : 0x00001400U */ + /* .. DIVISOR = 0xa */ + /* .. ==> 0XF8000154[13:8] = 0x0000000AU */ + /* .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */ /* .. */ - EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00001402U), + EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A02U), /* .. .. START: TRACE CLOCK */ /* .. .. FINISH: TRACE CLOCK */ /* .. .. CLKACT = 0x1 */ @@ -339,39 +339,39 @@ unsigned long ps7_clock_init_data_3_0[] = { /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ /* .. .. */ EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U), - /* .. .. SRCSEL = 0x3 */ - /* .. .. ==> 0XF8000180[5:4] = 0x00000003U */ - /* .. .. ==> MASK : 0x00000030U VAL : 0x00000030U */ - /* .. .. DIVISOR0 = 0x6 */ - /* .. .. ==> 0XF8000180[13:8] = 0x00000006U */ - /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000600U */ + /* .. .. SRCSEL = 0x0 */ + /* .. .. ==> 0XF8000180[5:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. .. DIVISOR0 = 0x7 */ + /* .. .. ==> 0XF8000180[13:8] = 0x00000007U */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000700U */ /* .. .. DIVISOR1 = 0x1 */ /* .. .. ==> 0XF8000180[25:20] = 0x00000001U */ /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ /* .. .. */ - EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100630U), - /* .. .. SRCSEL = 0x2 */ - /* .. .. ==> 0XF8000190[5:4] = 0x00000002U */ - /* .. .. ==> MASK : 0x00000030U VAL : 0x00000020U */ - /* .. .. DIVISOR0 = 0x35 */ - /* .. .. ==> 0XF8000190[13:8] = 0x00000035U */ - /* .. .. ==> MASK : 0x00003F00U VAL : 0x00003500U */ - /* .. .. DIVISOR1 = 0x2 */ - /* .. .. ==> 0XF8000190[25:20] = 0x00000002U */ - /* .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00203520U), + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100700U), + /* .. .. SRCSEL = 0x0 */ + /* .. .. ==> 0XF8000190[5:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. .. DIVISOR0 = 0x5 */ + /* .. .. ==> 0XF8000190[13:8] = 0x00000005U */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U */ + /* .. .. DIVISOR1 = 0x1 */ + /* .. .. ==> 0XF8000190[25:20] = 0x00000001U */ + /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100500U), /* .. .. SRCSEL = 0x0 */ /* .. .. ==> 0XF80001A0[5:4] = 0x00000000U */ /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ - /* .. .. DIVISOR0 = 0xa */ - /* .. .. ==> 0XF80001A0[13:8] = 0x0000000AU */ - /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */ + /* .. .. DIVISOR0 = 0x14 */ + /* .. .. ==> 0XF80001A0[13:8] = 0x00000014U */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U */ /* .. .. DIVISOR1 = 0x1 */ /* .. .. ==> 0XF80001A0[25:20] = 0x00000001U */ /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ /* .. .. */ - EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00100A00U), + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U), /* .. .. CLK_621_TRUE = 0x1 */ /* .. .. ==> 0XF80001C4[0:0] = 0x00000001U */ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ @@ -667,9 +667,9 @@ unsigned long ps7_ddr_init_data_3_0[] = { /* .. .. reg_ddrc_burst_rdwr = 0x4 */ /* .. .. ==> 0XF8006034[3:0] = 0x00000004U */ /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U */ - /* .. .. reg_ddrc_pre_cke_x1024 = 0x101 */ - /* .. .. ==> 0XF8006034[13:4] = 0x00000101U */ - /* .. .. ==> MASK : 0x00003FF0U VAL : 0x00001010U */ + /* .. .. reg_ddrc_pre_cke_x1024 = 0x167 */ + /* .. .. ==> 0XF8006034[13:4] = 0x00000167U */ + /* .. .. ==> MASK : 0x00003FF0U VAL : 0x00001670U */ /* .. .. reg_ddrc_post_cke_x1024 = 0x1 */ /* .. .. ==> 0XF8006034[25:16] = 0x00000001U */ /* .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U */ @@ -677,7 +677,7 @@ unsigned long ps7_ddr_init_data_3_0[] = { /* .. .. ==> 0XF8006034[28:28] = 0x00000000U */ /* .. .. ==> MASK : 0x10000000U VAL : 0x00000000U */ /* .. .. */ - EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011014U), + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011674U), /* .. .. reg_ddrc_force_low_pri_n = 0x0 */ /* .. .. ==> 0XF8006038[0:0] = 0x00000000U */ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ @@ -2020,6 +2020,35 @@ unsigned long ps7_mio_init_data_3_0[] = { /* .. FINISH: DDRIOB SETTINGS */ /* .. START: MIO PROGRAMMING */ /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000700[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000700[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000700[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000700[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000700[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000700[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000700[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000700[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000700[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ /* .. ==> 0XF8000704[0:0] = 0x00000000U */ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ /* .. L0_SEL = 1 */ @@ -2194,6 +2223,267 @@ unsigned long ps7_mio_init_data_3_0[] = { /* .. */ EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U), /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800071C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF800071C[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800071C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800071C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800071C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF800071C[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF800071C[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800071C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800071C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000720[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000720[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000720[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000720[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000720[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000720[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000720[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000720[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000720[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000724[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000724[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000724[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000724[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000724[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000724[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000724[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000724[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000724[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000728[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000728[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000728[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000728[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000728[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000728[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000728[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000728[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000728[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800072C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF800072C[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800072C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800072C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800072C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF800072C[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF800072C[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF800072C[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800072C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000730[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000730[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000730[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000730[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000730[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000730[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000730[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000730[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000730[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000734[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000734[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000734[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000734[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000734[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000734[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000734[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000734[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000734[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000738[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000738[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000738[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000738[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000738[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000738[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000738[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000738[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000738[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800073C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF800073C[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800073C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800073C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800073C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF800073C[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF800073C[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF800073C[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800073C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ /* .. ==> 0XF8000740[0:0] = 0x00000000U */ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ /* .. L0_SEL = 1 */ @@ -3063,6 +3353,35 @@ unsigned long ps7_mio_init_data_3_0[] = { /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ /* .. */ EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007B8[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007B8[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007B8[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007B8[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF80007B8[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007B8[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007B8[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF80007B8[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007B8[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00001200U), /* .. TRI_ENABLE = 1 */ /* .. ==> 0XF80007BC[0:0] = 0x00000001U */ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ @@ -3139,6 +3458,64 @@ unsigned long ps7_mio_init_data_3_0[] = { /* .. */ EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x000002E1U), /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007C8[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007C8[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007C8[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007C8[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF80007C8[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007C8[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007C8[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007C8[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007C8[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00000200U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007CC[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007CC[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007CC[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007CC[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF80007CC[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007CC[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007CC[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007CC[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007CC[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00000200U), + /* .. TRI_ENABLE = 0 */ /* .. ==> 0XF80007D0[0:0] = 0x00000000U */ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ /* .. L0_SEL = 0 */ @@ -3277,11 +3654,11 @@ unsigned long ps7_peripherals_init_data_3_0[] = { /* .. ==> MASK : 0x000000FFU VAL : 0x00000006U */ /* .. */ EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U), - /* .. CD = 0x3e */ - /* .. ==> 0XE0001018[15:0] = 0x0000003EU */ - /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU */ + /* .. CD = 0x7c */ + /* .. ==> 0XE0001018[15:0] = 0x0000007CU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU */ /* .. */ - EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000003EU), + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU), /* .. STPBRK = 0x0 */ /* .. ==> 0XE0001000[8:8] = 0x00000000U */ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ @@ -3329,29 +3706,6 @@ unsigned long ps7_peripherals_init_data_3_0[] = { /* .. */ EMIT_MASKWRITE(0XE0001004, 0x000003FFU, 0x00000020U), /* .. FINISH: UART REGISTERS */ - /* .. START: TPIU WIDTH IN CASE OF EMIO */ - /* .. .. START: TRACE LOCK ACCESS REGISTER */ - /* .. .. a = 0XC5ACCE55 */ - /* .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0xC5ACCE55U), - /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */ - /* .. .. START: TRACE CURRENT PORT SIZE */ - /* .. .. a = 2 */ - /* .. .. ==> 0XF8803004[31:0] = 0x00000002U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU, 0x00000002U), - /* .. .. FINISH: TRACE CURRENT PORT SIZE */ - /* .. .. START: TRACE LOCK ACCESS REGISTER */ - /* .. .. a = 0X0 */ - /* .. .. ==> 0XF8803FB0[31:0] = 0x00000000U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0x00000000U), - /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */ - /* .. FINISH: TPIU WIDTH IN CASE OF EMIO */ /* .. START: QSPI REGISTERS */ /* .. Holdb_dr = 1 */ /* .. ==> 0XE000D000[19:19] = 0x00000001U */ @@ -3390,24 +3744,50 @@ unsigned long ps7_peripherals_init_data_3_0[] = { /* .. .. .. .. START: DIR MODE BANK 0 */ /* .. .. .. .. FINISH: DIR MODE BANK 0 */ /* .. .. .. .. START: DIR MODE BANK 1 */ + /* .. .. .. .. DIRECTION_1 = 0x4000 */ + /* .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U */ + /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */ + /* .. .. .. .. */ + EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU, 0x00004000U), /* .. .. .. .. FINISH: DIR MODE BANK 1 */ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. MASK_1_LSW = 0xbfff */ + /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */ + /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */ + /* .. .. .. .. DATA_1_LSW = 0x4000 */ + /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */ + /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */ + /* .. .. .. .. */ + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U), /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */ /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */ /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. OP_ENABLE_1 = 0x4000 */ + /* .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U */ + /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */ + /* .. .. .. .. */ + EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU, 0x00004000U), /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */ /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. MASK_1_LSW = 0xbfff */ + /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */ + /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */ + /* .. .. .. .. DATA_1_LSW = 0x0 */ + /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U */ + /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U */ + /* .. .. .. .. */ + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF0000U), /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ @@ -3420,6 +3800,14 @@ unsigned long ps7_peripherals_init_data_3_0[] = { /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. MASK_1_LSW = 0xbfff */ + /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */ + /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */ + /* .. .. .. .. DATA_1_LSW = 0x4000 */ + /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */ + /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */ + /* .. .. .. .. */ + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U), /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ @@ -3660,29 +4048,6 @@ unsigned long ps7_post_config_3_0[] = { /* .. */ EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU), /* .. FINISH: ENABLING LEVEL SHIFTER */ - /* .. START: TPIU WIDTH IN CASE OF EMIO */ - /* .. .. START: TRACE LOCK ACCESS REGISTER */ - /* .. .. a = 0XC5ACCE55 */ - /* .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0xC5ACCE55U), - /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */ - /* .. .. START: TRACE CURRENT PORT SIZE */ - /* .. .. a = 2 */ - /* .. .. ==> 0XF8803004[31:0] = 0x00000002U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU, 0x00000002U), - /* .. .. FINISH: TRACE CURRENT PORT SIZE */ - /* .. .. START: TRACE LOCK ACCESS REGISTER */ - /* .. .. a = 0X0 */ - /* .. .. ==> 0XF8803FB0[31:0] = 0x00000000U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0x00000000U), - /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */ - /* .. FINISH: TPIU WIDTH IN CASE OF EMIO */ /* .. START: FPGA RESETS TO 0 */ /* .. reserved_3 = 0 */ /* .. ==> 0XF8000240[31:25] = 0x00000000U */ @@ -3759,6 +4124,8 @@ unsigned long ps7_post_config_3_0[] = { /* .. .. FINISH: AFI2 REGISTERS */ /* .. .. START: AFI3 REGISTERS */ /* .. .. FINISH: AFI3 REGISTERS */ + /* .. .. START: AFI2 SECURE REGISTER */ + /* .. .. FINISH: AFI2 SECURE REGISTER */ /* .. FINISH: AFI REGISTERS */ /* .. START: LOCK IT BACK */ /* .. LOCK_KEY = 0X767B */ @@ -4110,11 +4477,11 @@ unsigned long ps7_clock_init_data_2_0[] = { /* .. SRCSEL = 0x0 */ /* .. ==> 0XF8000154[5:4] = 0x00000000U */ /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */ - /* .. DIVISOR = 0x14 */ - /* .. ==> 0XF8000154[13:8] = 0x00000014U */ - /* .. ==> MASK : 0x00003F00U VAL : 0x00001400U */ + /* .. DIVISOR = 0xa */ + /* .. ==> 0XF8000154[13:8] = 0x0000000AU */ + /* .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */ /* .. */ - EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00001402U), + EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A02U), /* .. .. START: TRACE CLOCK */ /* .. .. FINISH: TRACE CLOCK */ /* .. .. CLKACT = 0x1 */ @@ -4139,39 +4506,39 @@ unsigned long ps7_clock_init_data_2_0[] = { /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ /* .. .. */ EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U), - /* .. .. SRCSEL = 0x3 */ - /* .. .. ==> 0XF8000180[5:4] = 0x00000003U */ - /* .. .. ==> MASK : 0x00000030U VAL : 0x00000030U */ - /* .. .. DIVISOR0 = 0x6 */ - /* .. .. ==> 0XF8000180[13:8] = 0x00000006U */ - /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000600U */ + /* .. .. SRCSEL = 0x0 */ + /* .. .. ==> 0XF8000180[5:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. .. DIVISOR0 = 0x7 */ + /* .. .. ==> 0XF8000180[13:8] = 0x00000007U */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000700U */ /* .. .. DIVISOR1 = 0x1 */ /* .. .. ==> 0XF8000180[25:20] = 0x00000001U */ /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ /* .. .. */ - EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100630U), - /* .. .. SRCSEL = 0x2 */ - /* .. .. ==> 0XF8000190[5:4] = 0x00000002U */ - /* .. .. ==> MASK : 0x00000030U VAL : 0x00000020U */ - /* .. .. DIVISOR0 = 0x35 */ - /* .. .. ==> 0XF8000190[13:8] = 0x00000035U */ - /* .. .. ==> MASK : 0x00003F00U VAL : 0x00003500U */ - /* .. .. DIVISOR1 = 0x2 */ - /* .. .. ==> 0XF8000190[25:20] = 0x00000002U */ - /* .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00203520U), + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100700U), + /* .. .. SRCSEL = 0x0 */ + /* .. .. ==> 0XF8000190[5:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. .. DIVISOR0 = 0x5 */ + /* .. .. ==> 0XF8000190[13:8] = 0x00000005U */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U */ + /* .. .. DIVISOR1 = 0x1 */ + /* .. .. ==> 0XF8000190[25:20] = 0x00000001U */ + /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100500U), /* .. .. SRCSEL = 0x0 */ /* .. .. ==> 0XF80001A0[5:4] = 0x00000000U */ /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ - /* .. .. DIVISOR0 = 0xa */ - /* .. .. ==> 0XF80001A0[13:8] = 0x0000000AU */ - /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */ + /* .. .. DIVISOR0 = 0x14 */ + /* .. .. ==> 0XF80001A0[13:8] = 0x00000014U */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U */ /* .. .. DIVISOR1 = 0x1 */ /* .. .. ==> 0XF80001A0[25:20] = 0x00000001U */ /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ /* .. .. */ - EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00100A00U), + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U), /* .. .. CLK_621_TRUE = 0x1 */ /* .. .. ==> 0XF80001C4[0:0] = 0x00000001U */ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ @@ -4491,9 +4858,9 @@ unsigned long ps7_ddr_init_data_2_0[] = { /* .. .. reg_ddrc_burst_rdwr = 0x4 */ /* .. .. ==> 0XF8006034[3:0] = 0x00000004U */ /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U */ - /* .. .. reg_ddrc_pre_cke_x1024 = 0x101 */ - /* .. .. ==> 0XF8006034[13:4] = 0x00000101U */ - /* .. .. ==> MASK : 0x00003FF0U VAL : 0x00001010U */ + /* .. .. reg_ddrc_pre_cke_x1024 = 0x167 */ + /* .. .. ==> 0XF8006034[13:4] = 0x00000167U */ + /* .. .. ==> MASK : 0x00003FF0U VAL : 0x00001670U */ /* .. .. reg_ddrc_post_cke_x1024 = 0x1 */ /* .. .. ==> 0XF8006034[25:16] = 0x00000001U */ /* .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U */ @@ -4501,7 +4868,7 @@ unsigned long ps7_ddr_init_data_2_0[] = { /* .. .. ==> 0XF8006034[28:28] = 0x00000000U */ /* .. .. ==> MASK : 0x10000000U VAL : 0x00000000U */ /* .. .. */ - EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011014U), + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011674U), /* .. .. reg_ddrc_force_low_pri_n = 0x0 */ /* .. .. ==> 0XF8006038[0:0] = 0x00000000U */ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ @@ -5981,6 +6348,35 @@ unsigned long ps7_mio_init_data_2_0[] = { /* .. FINISH: DDRIOB SETTINGS */ /* .. START: MIO PROGRAMMING */ /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000700[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000700[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000700[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000700[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000700[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000700[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000700[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000700[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000700[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ /* .. ==> 0XF8000704[0:0] = 0x00000000U */ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ /* .. L0_SEL = 1 */ @@ -6155,6 +6551,267 @@ unsigned long ps7_mio_init_data_2_0[] = { /* .. */ EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U), /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800071C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF800071C[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800071C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800071C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800071C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF800071C[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF800071C[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800071C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800071C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000720[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000720[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000720[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000720[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000720[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000720[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000720[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000720[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000720[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000724[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000724[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000724[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000724[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000724[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000724[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000724[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000724[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000724[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000728[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000728[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000728[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000728[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000728[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000728[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000728[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000728[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000728[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800072C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF800072C[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800072C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800072C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800072C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF800072C[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF800072C[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF800072C[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800072C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000730[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000730[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000730[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000730[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000730[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000730[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000730[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000730[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000730[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000734[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000734[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000734[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000734[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000734[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000734[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000734[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000734[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000734[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000738[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000738[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000738[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000738[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000738[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000738[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000738[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000738[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000738[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800073C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF800073C[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800073C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800073C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800073C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF800073C[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF800073C[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF800073C[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800073C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ /* .. ==> 0XF8000740[0:0] = 0x00000000U */ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ /* .. L0_SEL = 1 */ @@ -7024,6 +7681,35 @@ unsigned long ps7_mio_init_data_2_0[] = { /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ /* .. */ EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007B8[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007B8[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007B8[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007B8[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF80007B8[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007B8[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007B8[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF80007B8[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007B8[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00001200U), /* .. TRI_ENABLE = 1 */ /* .. ==> 0XF80007BC[0:0] = 0x00000001U */ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ @@ -7100,6 +7786,64 @@ unsigned long ps7_mio_init_data_2_0[] = { /* .. */ EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x000002E1U), /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007C8[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007C8[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007C8[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007C8[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF80007C8[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007C8[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007C8[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007C8[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007C8[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00000200U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007CC[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007CC[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007CC[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007CC[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF80007CC[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007CC[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007CC[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007CC[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007CC[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00000200U), + /* .. TRI_ENABLE = 0 */ /* .. ==> 0XF80007D0[0:0] = 0x00000000U */ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ /* .. L0_SEL = 0 */ @@ -7238,11 +7982,11 @@ unsigned long ps7_peripherals_init_data_2_0[] = { /* .. ==> MASK : 0x000000FFU VAL : 0x00000006U */ /* .. */ EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U), - /* .. CD = 0x3e */ - /* .. ==> 0XE0001018[15:0] = 0x0000003EU */ - /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU */ + /* .. CD = 0x7c */ + /* .. ==> 0XE0001018[15:0] = 0x0000007CU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU */ /* .. */ - EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000003EU), + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU), /* .. STPBRK = 0x0 */ /* .. ==> 0XE0001000[8:8] = 0x00000000U */ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ @@ -7296,29 +8040,6 @@ unsigned long ps7_peripherals_init_data_2_0[] = { /* .. */ EMIT_MASKWRITE(0XE0001004, 0x00000FFFU, 0x00000020U), /* .. FINISH: UART REGISTERS */ - /* .. START: TPIU WIDTH IN CASE OF EMIO */ - /* .. .. START: TRACE LOCK ACCESS REGISTER */ - /* .. .. a = 0XC5ACCE55 */ - /* .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0xC5ACCE55U), - /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */ - /* .. .. START: TRACE CURRENT PORT SIZE */ - /* .. .. a = 2 */ - /* .. .. ==> 0XF8803004[31:0] = 0x00000002U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU, 0x00000002U), - /* .. .. FINISH: TRACE CURRENT PORT SIZE */ - /* .. .. START: TRACE LOCK ACCESS REGISTER */ - /* .. .. a = 0X0 */ - /* .. .. ==> 0XF8803FB0[31:0] = 0x00000000U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0x00000000U), - /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */ - /* .. FINISH: TPIU WIDTH IN CASE OF EMIO */ /* .. START: QSPI REGISTERS */ /* .. Holdb_dr = 1 */ /* .. ==> 0XE000D000[19:19] = 0x00000001U */ @@ -7357,24 +8078,50 @@ unsigned long ps7_peripherals_init_data_2_0[] = { /* .. .. .. .. START: DIR MODE BANK 0 */ /* .. .. .. .. FINISH: DIR MODE BANK 0 */ /* .. .. .. .. START: DIR MODE BANK 1 */ + /* .. .. .. .. DIRECTION_1 = 0x4000 */ + /* .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U */ + /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */ + /* .. .. .. .. */ + EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU, 0x00004000U), /* .. .. .. .. FINISH: DIR MODE BANK 1 */ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. MASK_1_LSW = 0xbfff */ + /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */ + /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */ + /* .. .. .. .. DATA_1_LSW = 0x4000 */ + /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */ + /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */ + /* .. .. .. .. */ + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U), /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */ /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */ /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. OP_ENABLE_1 = 0x4000 */ + /* .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U */ + /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */ + /* .. .. .. .. */ + EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU, 0x00004000U), /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */ /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. MASK_1_LSW = 0xbfff */ + /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */ + /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */ + /* .. .. .. .. DATA_1_LSW = 0x0 */ + /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U */ + /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U */ + /* .. .. .. .. */ + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF0000U), /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ @@ -7387,6 +8134,14 @@ unsigned long ps7_peripherals_init_data_2_0[] = { /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. MASK_1_LSW = 0xbfff */ + /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */ + /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */ + /* .. .. .. .. DATA_1_LSW = 0x4000 */ + /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */ + /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */ + /* .. .. .. .. */ + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U), /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ @@ -7621,29 +8376,6 @@ unsigned long ps7_post_config_2_0[] = { /* .. */ EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU), /* .. FINISH: ENABLING LEVEL SHIFTER */ - /* .. START: TPIU WIDTH IN CASE OF EMIO */ - /* .. .. START: TRACE LOCK ACCESS REGISTER */ - /* .. .. a = 0XC5ACCE55 */ - /* .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0xC5ACCE55U), - /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */ - /* .. .. START: TRACE CURRENT PORT SIZE */ - /* .. .. a = 2 */ - /* .. .. ==> 0XF8803004[31:0] = 0x00000002U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU, 0x00000002U), - /* .. .. FINISH: TRACE CURRENT PORT SIZE */ - /* .. .. START: TRACE LOCK ACCESS REGISTER */ - /* .. .. a = 0X0 */ - /* .. .. ==> 0XF8803FB0[31:0] = 0x00000000U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0x00000000U), - /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */ - /* .. FINISH: TPIU WIDTH IN CASE OF EMIO */ /* .. START: FPGA RESETS TO 0 */ /* .. reserved_3 = 0 */ /* .. ==> 0XF8000240[31:25] = 0x00000000U */ @@ -8071,11 +8803,11 @@ unsigned long ps7_clock_init_data_1_0[] = { /* .. SRCSEL = 0x0 */ /* .. ==> 0XF8000154[5:4] = 0x00000000U */ /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */ - /* .. DIVISOR = 0x14 */ - /* .. ==> 0XF8000154[13:8] = 0x00000014U */ - /* .. ==> MASK : 0x00003F00U VAL : 0x00001400U */ + /* .. DIVISOR = 0xa */ + /* .. ==> 0XF8000154[13:8] = 0x0000000AU */ + /* .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */ /* .. */ - EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00001402U), + EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A02U), /* .. .. START: TRACE CLOCK */ /* .. .. FINISH: TRACE CLOCK */ /* .. .. CLKACT = 0x1 */ @@ -8100,39 +8832,39 @@ unsigned long ps7_clock_init_data_1_0[] = { /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ /* .. .. */ EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U), - /* .. .. SRCSEL = 0x3 */ - /* .. .. ==> 0XF8000180[5:4] = 0x00000003U */ - /* .. .. ==> MASK : 0x00000030U VAL : 0x00000030U */ - /* .. .. DIVISOR0 = 0x6 */ - /* .. .. ==> 0XF8000180[13:8] = 0x00000006U */ - /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000600U */ + /* .. .. SRCSEL = 0x0 */ + /* .. .. ==> 0XF8000180[5:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. .. DIVISOR0 = 0x7 */ + /* .. .. ==> 0XF8000180[13:8] = 0x00000007U */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000700U */ /* .. .. DIVISOR1 = 0x1 */ /* .. .. ==> 0XF8000180[25:20] = 0x00000001U */ /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ /* .. .. */ - EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100630U), - /* .. .. SRCSEL = 0x2 */ - /* .. .. ==> 0XF8000190[5:4] = 0x00000002U */ - /* .. .. ==> MASK : 0x00000030U VAL : 0x00000020U */ - /* .. .. DIVISOR0 = 0x35 */ - /* .. .. ==> 0XF8000190[13:8] = 0x00000035U */ - /* .. .. ==> MASK : 0x00003F00U VAL : 0x00003500U */ - /* .. .. DIVISOR1 = 0x2 */ - /* .. .. ==> 0XF8000190[25:20] = 0x00000002U */ - /* .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00203520U), + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100700U), + /* .. .. SRCSEL = 0x0 */ + /* .. .. ==> 0XF8000190[5:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. .. DIVISOR0 = 0x5 */ + /* .. .. ==> 0XF8000190[13:8] = 0x00000005U */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U */ + /* .. .. DIVISOR1 = 0x1 */ + /* .. .. ==> 0XF8000190[25:20] = 0x00000001U */ + /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100500U), /* .. .. SRCSEL = 0x0 */ /* .. .. ==> 0XF80001A0[5:4] = 0x00000000U */ /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ - /* .. .. DIVISOR0 = 0xa */ - /* .. .. ==> 0XF80001A0[13:8] = 0x0000000AU */ - /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */ + /* .. .. DIVISOR0 = 0x14 */ + /* .. .. ==> 0XF80001A0[13:8] = 0x00000014U */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U */ /* .. .. DIVISOR1 = 0x1 */ /* .. .. ==> 0XF80001A0[25:20] = 0x00000001U */ /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ /* .. .. */ - EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00100A00U), + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U), /* .. .. CLK_621_TRUE = 0x1 */ /* .. .. ==> 0XF80001C4[0:0] = 0x00000001U */ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ @@ -8452,9 +9184,9 @@ unsigned long ps7_ddr_init_data_1_0[] = { /* .. .. reg_ddrc_burst_rdwr = 0x4 */ /* .. .. ==> 0XF8006034[3:0] = 0x00000004U */ /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U */ - /* .. .. reg_ddrc_pre_cke_x1024 = 0x101 */ - /* .. .. ==> 0XF8006034[13:4] = 0x00000101U */ - /* .. .. ==> MASK : 0x00003FF0U VAL : 0x00001010U */ + /* .. .. reg_ddrc_pre_cke_x1024 = 0x167 */ + /* .. .. ==> 0XF8006034[13:4] = 0x00000167U */ + /* .. .. ==> MASK : 0x00003FF0U VAL : 0x00001670U */ /* .. .. reg_ddrc_post_cke_x1024 = 0x1 */ /* .. .. ==> 0XF8006034[25:16] = 0x00000001U */ /* .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U */ @@ -8462,7 +9194,7 @@ unsigned long ps7_ddr_init_data_1_0[] = { /* .. .. ==> 0XF8006034[28:28] = 0x00000000U */ /* .. .. ==> MASK : 0x10000000U VAL : 0x00000000U */ /* .. .. */ - EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011014U), + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011674U), /* .. .. reg_ddrc_force_low_pri_n = 0x0 */ /* .. .. ==> 0XF8006038[0:0] = 0x00000000U */ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ @@ -9875,6 +10607,35 @@ unsigned long ps7_mio_init_data_1_0[] = { /* .. FINISH: DDRIOB SETTINGS */ /* .. START: MIO PROGRAMMING */ /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000700[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000700[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000700[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000700[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000700[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000700[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000700[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000700[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000700[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ /* .. ==> 0XF8000704[0:0] = 0x00000000U */ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ /* .. L0_SEL = 1 */ @@ -10049,6 +10810,267 @@ unsigned long ps7_mio_init_data_1_0[] = { /* .. */ EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U), /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800071C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF800071C[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800071C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800071C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800071C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF800071C[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF800071C[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800071C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800071C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000720[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000720[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000720[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000720[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000720[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000720[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000720[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000720[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000720[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000724[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000724[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000724[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000724[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000724[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000724[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000724[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000724[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000724[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000728[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000728[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000728[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000728[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000728[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000728[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000728[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000728[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000728[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800072C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF800072C[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800072C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800072C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800072C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF800072C[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF800072C[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF800072C[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800072C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000730[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000730[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000730[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000730[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000730[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000730[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000730[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000730[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000730[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000734[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000734[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000734[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000734[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000734[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000734[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000734[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000734[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000734[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000738[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000738[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000738[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000738[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000738[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000738[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000738[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000738[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000738[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800073C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF800073C[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800073C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800073C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800073C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF800073C[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF800073C[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF800073C[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800073C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ /* .. ==> 0XF8000740[0:0] = 0x00000000U */ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ /* .. L0_SEL = 1 */ @@ -10918,6 +11940,35 @@ unsigned long ps7_mio_init_data_1_0[] = { /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ /* .. */ EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007B8[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007B8[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007B8[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007B8[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF80007B8[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007B8[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007B8[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF80007B8[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007B8[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00001200U), /* .. TRI_ENABLE = 1 */ /* .. ==> 0XF80007BC[0:0] = 0x00000001U */ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ @@ -10994,6 +12045,64 @@ unsigned long ps7_mio_init_data_1_0[] = { /* .. */ EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x000002E1U), /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007C8[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007C8[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007C8[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007C8[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF80007C8[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007C8[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007C8[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007C8[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007C8[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00000200U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007CC[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007CC[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007CC[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007CC[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF80007CC[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007CC[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007CC[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007CC[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007CC[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00000200U), + /* .. TRI_ENABLE = 0 */ /* .. ==> 0XF80007D0[0:0] = 0x00000000U */ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ /* .. L0_SEL = 0 */ @@ -11132,11 +12241,11 @@ unsigned long ps7_peripherals_init_data_1_0[] = { /* .. ==> MASK : 0x000000FFU VAL : 0x00000006U */ /* .. */ EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U), - /* .. CD = 0x3e */ - /* .. ==> 0XE0001018[15:0] = 0x0000003EU */ - /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU */ + /* .. CD = 0x7c */ + /* .. ==> 0XE0001018[15:0] = 0x0000007CU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU */ /* .. */ - EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000003EU), + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU), /* .. STPBRK = 0x0 */ /* .. ==> 0XE0001000[8:8] = 0x00000000U */ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ @@ -11190,29 +12299,6 @@ unsigned long ps7_peripherals_init_data_1_0[] = { /* .. */ EMIT_MASKWRITE(0XE0001004, 0x00000FFFU, 0x00000020U), /* .. FINISH: UART REGISTERS */ - /* .. START: TPIU WIDTH IN CASE OF EMIO */ - /* .. .. START: TRACE LOCK ACCESS REGISTER */ - /* .. .. a = 0XC5ACCE55 */ - /* .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0xC5ACCE55U), - /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */ - /* .. .. START: TRACE CURRENT PORT SIZE */ - /* .. .. a = 2 */ - /* .. .. ==> 0XF8803004[31:0] = 0x00000002U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU, 0x00000002U), - /* .. .. FINISH: TRACE CURRENT PORT SIZE */ - /* .. .. START: TRACE LOCK ACCESS REGISTER */ - /* .. .. a = 0X0 */ - /* .. .. ==> 0XF8803FB0[31:0] = 0x00000000U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0x00000000U), - /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */ - /* .. FINISH: TPIU WIDTH IN CASE OF EMIO */ /* .. START: QSPI REGISTERS */ /* .. Holdb_dr = 1 */ /* .. ==> 0XE000D000[19:19] = 0x00000001U */ @@ -11251,24 +12337,50 @@ unsigned long ps7_peripherals_init_data_1_0[] = { /* .. .. .. .. START: DIR MODE BANK 0 */ /* .. .. .. .. FINISH: DIR MODE BANK 0 */ /* .. .. .. .. START: DIR MODE BANK 1 */ + /* .. .. .. .. DIRECTION_1 = 0x4000 */ + /* .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U */ + /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */ + /* .. .. .. .. */ + EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU, 0x00004000U), /* .. .. .. .. FINISH: DIR MODE BANK 1 */ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. MASK_1_LSW = 0xbfff */ + /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */ + /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */ + /* .. .. .. .. DATA_1_LSW = 0x4000 */ + /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */ + /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */ + /* .. .. .. .. */ + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U), /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */ /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */ /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. OP_ENABLE_1 = 0x4000 */ + /* .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U */ + /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */ + /* .. .. .. .. */ + EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU, 0x00004000U), /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */ /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. MASK_1_LSW = 0xbfff */ + /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */ + /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */ + /* .. .. .. .. DATA_1_LSW = 0x0 */ + /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U */ + /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U */ + /* .. .. .. .. */ + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF0000U), /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ @@ -11281,6 +12393,14 @@ unsigned long ps7_peripherals_init_data_1_0[] = { /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. MASK_1_LSW = 0xbfff */ + /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */ + /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */ + /* .. .. .. .. DATA_1_LSW = 0x4000 */ + /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */ + /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */ + /* .. .. .. .. */ + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U), /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ @@ -11515,29 +12635,6 @@ unsigned long ps7_post_config_1_0[] = { /* .. */ EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU), /* .. FINISH: ENABLING LEVEL SHIFTER */ - /* .. START: TPIU WIDTH IN CASE OF EMIO */ - /* .. .. START: TRACE LOCK ACCESS REGISTER */ - /* .. .. a = 0XC5ACCE55 */ - /* .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0xC5ACCE55U), - /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */ - /* .. .. START: TRACE CURRENT PORT SIZE */ - /* .. .. a = 2 */ - /* .. .. ==> 0XF8803004[31:0] = 0x00000002U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU, 0x00000002U), - /* .. .. FINISH: TRACE CURRENT PORT SIZE */ - /* .. .. START: TRACE LOCK ACCESS REGISTER */ - /* .. .. a = 0X0 */ - /* .. .. ==> 0XF8803FB0[31:0] = 0x00000000U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0x00000000U), - /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */ - /* .. FINISH: TPIU WIDTH IN CASE OF EMIO */ /* .. START: FPGA RESETS TO 0 */ /* .. reserved_3 = 0 */ /* .. ==> 0XF8000240[31:25] = 0x00000000U */ diff --git a/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.h b/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.h index 62b8a5846b..22d9fd9250 100644 --- a/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.h +++ b/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.h @@ -62,7 +62,7 @@ extern unsigned long *ps7_peripherals_init_data; #define USB0_FREQ 60000000 #define USB1_FREQ 60000000 #define SDIO_FREQ 50000000 -#define UART_FREQ 50000000 +#define UART_FREQ 100000000 #define SPI_FREQ 10000000 #define I2C_FREQ 108333336 #define WDT_FREQ 108333336 @@ -71,9 +71,10 @@ extern unsigned long *ps7_peripherals_init_data; #define PCAP_FREQ 200000000 #define TPIU_FREQ 200000000 #define FPGA0_FREQ 100000000 -#define FPGA1_FREQ 175000000 -#define FPGA2_FREQ 12264151 -#define FPGA3_FREQ 100000000 +#define FPGA1_FREQ 142857132 +#define FPGA2_FREQ 200000000 +#define FPGA3_FREQ 50000000 + /* For delay calculation using global registers*/ #define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 diff --git a/board/xilinx/zynqmp/MAINTAINERS b/board/xilinx/zynqmp/MAINTAINERS index 20ca6522e5..69edbf21f9 100644 --- a/board/xilinx/zynqmp/MAINTAINERS +++ b/board/xilinx/zynqmp/MAINTAINERS @@ -1,7 +1,6 @@ -XILINX_ZYNQMP_EP BOARD +XILINX_ZYNQMP BOARDS M: Michal Simek <michal.simek@xilinx.com> S: Maintained F: board/xilinx/zynqmp/ -F: include/configs/xilinx_zynqmp.h -F: include/configs/xilinx_zynqmp_ep.h -F: configs/xilinx_zynqmp_ep_defconfig +F: include/configs/xilinx_zynqmp* +F: configs/xilinx_zynqmp* diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 44d347ed3b..087578cb6b 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -7,6 +7,7 @@ #include <common.h> #include <netdev.h> +#include <sata.h> #include <ahci.h> #include <scsi.h> #include <asm/arch/clk.h> @@ -50,12 +51,133 @@ int board_early_init_r(void) return 0; } +#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE) +/* + * fdt_get_reg - Fill buffer by information from DT + */ +static phys_size_t fdt_get_reg(const void *fdt, int nodeoffset, void *buf, + const u32 *cell, int n) +{ + int i = 0, b, banks; + int parent_offset = fdt_parent_offset(fdt, nodeoffset); + int address_cells = fdt_address_cells(fdt, parent_offset); + int size_cells = fdt_size_cells(fdt, parent_offset); + char *p = buf; + phys_addr_t val; + phys_size_t vals; + + debug("%s: addr_cells=%x, size_cell=%x, buf=%p, cell=%p\n", + __func__, address_cells, size_cells, buf, cell); + + /* Check memory bank setup */ + banks = n % (address_cells + size_cells); + if (banks) + panic("Incorrect memory setup cells=%d, ac=%d, sc=%d\n", + n, address_cells, size_cells); + + banks = n / (address_cells + size_cells); + + for (b = 0; b < banks; b++) { + debug("%s: Bank #%d:\n", __func__, b); + if (address_cells == 2) { + val = cell[i + 1]; + val <<= 32; + val |= cell[i]; + val = fdt64_to_cpu(val); + debug("%s: addr64=%llx, ptr=%p, cell=%p\n", + __func__, val, p, &cell[i]); + *(phys_addr_t *)p = val; + } else { + debug("%s: addr32=%x, ptr=%p\n", + __func__, fdt32_to_cpu(cell[i]), p); + *(phys_addr_t *)p = fdt32_to_cpu(cell[i]); + } + p += sizeof(phys_addr_t); + i += address_cells; + + debug("%s: pa=%p, i=%x, size=%zu\n", __func__, p, i, + sizeof(phys_addr_t)); + + if (size_cells == 2) { + vals = cell[i + 1]; + vals <<= 32; + vals |= cell[i]; + vals = fdt64_to_cpu(vals); + + debug("%s: size64=%llx, ptr=%p, cell=%p\n", + __func__, vals, p, &cell[i]); + *(phys_size_t *)p = vals; + } else { + debug("%s: size32=%x, ptr=%p\n", + __func__, fdt32_to_cpu(cell[i]), p); + *(phys_size_t *)p = fdt32_to_cpu(cell[i]); + } + p += sizeof(phys_size_t); + i += size_cells; + + debug("%s: ps=%p, i=%x, size=%zu\n", + __func__, p, i, sizeof(phys_size_t)); + } + + /* Return the first address size */ + return *(phys_size_t *)((char *)buf + sizeof(phys_addr_t)); +} + +#define FDT_REG_SIZE sizeof(u32) +/* Temp location for sharing data for storing */ +/* Up to 64-bit address + 64-bit size */ +static u8 tmp[CONFIG_NR_DRAM_BANKS * 16]; + +void dram_init_banksize(void) +{ + int bank; + + memcpy(&gd->bd->bi_dram[0], &tmp, sizeof(tmp)); + + for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { + debug("Bank #%d: start %llx\n", bank, + (unsigned long long)gd->bd->bi_dram[bank].start); + debug("Bank #%d: size %llx\n", bank, + (unsigned long long)gd->bd->bi_dram[bank].size); + } +} + +int dram_init(void) +{ + int node, len; + const void *blob = gd->fdt_blob; + const u32 *cell; + + memset(&tmp, 0, sizeof(tmp)); + + /* find or create "/memory" node. */ + node = fdt_subnode_offset(blob, 0, "memory"); + if (node < 0) { + printf("%s: Can't get memory node\n", __func__); + return node; + } + + /* Get pointer to cells and lenght of it */ + cell = fdt_getprop(blob, node, "reg", &len); + if (!cell) { + printf("%s: Can't get reg property\n", __func__); + return -1; + } + + gd->ram_size = fdt_get_reg(blob, node, &tmp, cell, len / FDT_REG_SIZE); + + debug("%s: Initial DRAM size %llx\n", __func__, gd->ram_size); + + return 0; +} +#else int dram_init(void) { gd->ram_size = CONFIG_SYS_SDRAM_SIZE; return 0; } +#endif void reset_cpu(ulong addr) { @@ -64,6 +186,9 @@ void reset_cpu(ulong addr) #ifdef CONFIG_SCSI_AHCI_PLAT void scsi_init(void) { +#if defined(CONFIG_SATA_CEVA) + init_sata(0); +#endif ahci_init((void __iomem *)ZYNQMP_SATA_BASEADDR); scsi_scan(1); } diff --git a/configs/xilinx_zynqmp_ep_defconfig b/configs/xilinx_zynqmp_ep_defconfig index 33f29afab8..91ae10ab21 100644 --- a/configs/xilinx_zynqmp_ep_defconfig +++ b/configs/xilinx_zynqmp_ep_defconfig @@ -1,10 +1,12 @@ CONFIG_ARM=y +CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_ep" CONFIG_ARCH_ZYNQMP=y CONFIG_ZYNQMP_USB=y CONFIG_SYS_TEXT_BASE=0x8000000 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-ep108" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y +CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="ZynqMP> " # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_IMLS is not set diff --git a/configs/zynq_microzed_defconfig b/configs/zynq_microzed_defconfig index 4c5152fa73..1d70e43df0 100644 --- a/configs/zynq_microzed_defconfig +++ b/configs/zynq_microzed_defconfig @@ -15,6 +15,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_ZYNQ_SDHCI=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig index 4a59890ff3..d2f81101b9 100644 --- a/configs/zynq_zybo_defconfig +++ b/configs/zynq_zybo_defconfig @@ -15,6 +15,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_ZYNQ_SDHCI=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_ZYNQ_GEM=y CONFIG_DEBUG_UART=y diff --git a/drivers/block/Makefile b/drivers/block/Makefile index b4cbb09344..a43492f208 100644 --- a/drivers/block/Makefile +++ b/drivers/block/Makefile @@ -16,6 +16,7 @@ obj-$(CONFIG_LIBATA) += libata.o obj-$(CONFIG_MVSATA_IDE) += mvsata_ide.o obj-$(CONFIG_MX51_PATA) += mxc_ata.o obj-$(CONFIG_PATA_BFIN) += pata_bfin.o +obj-$(CONFIG_SATA_CEVA) += sata_ceva.o obj-$(CONFIG_SATA_DWC) += sata_dwc.o obj-$(CONFIG_SATA_MV) += sata_mv.o obj-$(CONFIG_SATA_SIL3114) += sata_sil3114.o diff --git a/drivers/block/sata_ceva.c b/drivers/block/sata_ceva.c new file mode 100644 index 0000000000..dcc3b90b17 --- /dev/null +++ b/drivers/block/sata_ceva.c @@ -0,0 +1,113 @@ +/* + * (C) Copyright 2015 - 2016 Xilinx, Inc. + * Michal Simek <michal.simek@xilinx.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <netdev.h> +#include <ahci.h> +#include <scsi.h> +#include <asm/arch/hardware.h> + +#include <asm/io.h> + +/* Vendor Specific Register Offsets */ +#define AHCI_VEND_PCFG 0xA4 +#define AHCI_VEND_PPCFG 0xA8 +#define AHCI_VEND_PP2C 0xAC +#define AHCI_VEND_PP3C 0xB0 +#define AHCI_VEND_PP4C 0xB4 +#define AHCI_VEND_PP5C 0xB8 +#define AHCI_VEND_PAXIC 0xC0 +#define AHCI_VEND_PTC 0xC8 + +/* Vendor Specific Register bit definitions */ +#define PAXIC_ADBW_BW64 0x1 +#define PAXIC_MAWIDD (1 << 8) +#define PAXIC_MARIDD (1 << 16) +#define PAXIC_OTL (0x4 << 20) + +#define PCFG_TPSS_VAL (0x32 << 16) +#define PCFG_TPRS_VAL (0x2 << 12) +#define PCFG_PAD_VAL 0x2 + +#define PPCFG_TTA 0x1FFFE +#define PPCFG_PSSO_EN (1 << 28) +#define PPCFG_PSS_EN (1 << 29) +#define PPCFG_ESDF_EN (1 << 31) + +#define PP2C_CIBGMN 0x0F +#define PP2C_CIBGMX (0x25 << 8) +#define PP2C_CIBGN (0x18 << 16) +#define PP2C_CINMP (0x29 << 24) + +#define PP3C_CWBGMN 0x04 +#define PP3C_CWBGMX (0x0B << 8) +#define PP3C_CWBGN (0x08 << 16) +#define PP3C_CWNMP (0x0F << 24) + +#define PP4C_BMX 0x0a +#define PP4C_BNM (0x08 << 8) +#define PP4C_SFD (0x4a << 16) +#define PP4C_PTST (0x06 << 24) + +#define PP5C_RIT 0x60216 +#define PP5C_RCT (0x7f0 << 20) + +#define PTC_RX_WM_VAL 0x40 +#define PTC_RSVD (1 << 27) + +#define PORT0_BASE 0x100 +#define PORT1_BASE 0x180 + +/* Port Control Register Bit Definitions */ +#define PORT_SCTL_SPD_GEN3 (0x3 << 4) +#define PORT_SCTL_SPD_GEN2 (0x2 << 4) +#define PORT_SCTL_SPD_GEN1 (0x1 << 4) +#define PORT_SCTL_IPM (0x3 << 8) + +#define PORT_BASE 0x100 +#define PORT_OFFSET 0x80 +#define NR_PORTS 2 +#define DRV_NAME "ahci-ceva" +#define CEVA_FLAG_BROKEN_GEN2 1 + +int init_sata(int dev) +{ + ulong tmp; + ulong mmio = ZYNQMP_SATA_BASEADDR; + int i; + + /* + * AXI Data bus width to 64 + * Set Mem Addr Read, Write ID for data transfers + * Transfer limit to 72 DWord + */ + tmp = PAXIC_ADBW_BW64 | PAXIC_MAWIDD | PAXIC_MARIDD | PAXIC_OTL; + writel(tmp, mmio + AHCI_VEND_PAXIC); + + /* Set AHCI Enable */ + tmp = readl(mmio + HOST_CTL); + tmp |= HOST_AHCI_EN; + writel(tmp, mmio + HOST_CTL); + + for (i = 0; i < NR_PORTS; i++) { + /* TPSS TPRS scalars, CISE and Port Addr */ + tmp = PCFG_TPSS_VAL | PCFG_TPRS_VAL | (PCFG_PAD_VAL + i); + writel(tmp, mmio + AHCI_VEND_PCFG); + + /* Port Phy Cfg register enables */ + tmp = PPCFG_TTA | PPCFG_PSS_EN | PPCFG_ESDF_EN; + writel(tmp, mmio + AHCI_VEND_PPCFG); + + /* Rx Watermark setting */ + tmp = PTC_RX_WM_VAL | PTC_RSVD; + writel(tmp, mmio + AHCI_VEND_PTC); + + /* Default to Gen 2 Speed and Gen 1 if Gen2 is broken */ + tmp = PORT_SCTL_SPD_GEN3 | PORT_SCTL_IPM; + writel(tmp, mmio + PORT_SCR_CTL + PORT_BASE + PORT_OFFSET * i); + } + return 0; +} diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index 9e4d4927e6..1e299b97b9 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -25,4 +25,5 @@ obj-$(CONFIG_PHY_REALTEK) += realtek.o obj-$(CONFIG_PHY_SMSC) += smsc.o obj-$(CONFIG_PHY_TERANETICS) += teranetics.o obj-$(CONFIG_PHY_TI) += ti.o +obj-$(CONFIG_PHY_XILINX) += xilinx_phy.o obj-$(CONFIG_PHY_VITESSE) += vitesse.o diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index 17866a244b..23c82bb36e 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -503,6 +503,9 @@ int phy_init(void) #ifdef CONFIG_PHY_VITESSE phy_vitesse_init(); #endif +#ifdef CONFIG_PHY_XILINX + phy_xilinx_init(); +#endif return 0; } diff --git a/drivers/net/phy/ti.c b/drivers/net/phy/ti.c index c3912d52f3..937426bc85 100644 --- a/drivers/net/phy/ti.c +++ b/drivers/net/phy/ti.c @@ -12,6 +12,8 @@ #define MII_DP83867_PHYCTRL 0x10 #define MII_DP83867_MICR 0x12 +#define MII_DP83867_CFG2 0x14 +#define MII_DP83867_BISCR 0x16 #define DP83867_CTRL 0x1f /* Extended Registers */ @@ -43,10 +45,22 @@ #define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14 #define DP83867_MDI_CROSSOVER 5 #define DP83867_MDI_CROSSOVER_AUTO 2 +#define DP83867_MDI_CROSSOVER_MDIX 2 +#define DP83867_PHYCTRL_SGMIIEN 0x0800 +#define DP83867_PHYCTRL_RXFIFO_SHIFT 12 +#define DP83867_PHYCTRL_TXFIFO_SHIFT 14 /* RGMIIDCTL bits */ #define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4 +/* CFG2 bits */ +#define MII_DP83867_CFG2_SPEEDOPT_10EN 0x0040 +#define MII_DP83867_CFG2_SGMII_AUTONEGEN 0x0080 +#define MII_DP83867_CFG2_SPEEDOPT_ENH 0x0100 +#define MII_DP83867_CFG2_SPEEDOPT_CNT 0x0800 +#define MII_DP83867_CFG2_SPEEDOPT_INTLOW 0x2000 +#define MII_DP83867_CFG2_MASK 0x003F + #define MII_MMD_CTRL 0x0d /* MMD Access Control Register */ #define MII_MMD_DATA 0x0e /* MMD Access Data Register */ @@ -141,7 +155,7 @@ static inline bool phy_interface_is_rgmii(struct phy_device *phydev) static int dp83867_config(struct phy_device *phydev) { - unsigned int val, delay; + unsigned int val, delay, cfg2; int ret; /* Restart the PHY. */ @@ -155,6 +169,29 @@ static int dp83867_config(struct phy_device *phydev) (FIFO_DEPTH << DP83867_PHYCR_FIFO_DEPTH_SHIFT)); if (ret) return ret; + } else { + phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, + (BMCR_ANENABLE | BMCR_FULLDPLX | BMCR_SPEED1000)); + + cfg2 = phy_read(phydev, phydev->addr, MII_DP83867_CFG2); + cfg2 &= MII_DP83867_CFG2_MASK; + cfg2 |= (MII_DP83867_CFG2_SPEEDOPT_10EN | + MII_DP83867_CFG2_SGMII_AUTONEGEN | + MII_DP83867_CFG2_SPEEDOPT_ENH | + MII_DP83867_CFG2_SPEEDOPT_CNT | + MII_DP83867_CFG2_SPEEDOPT_INTLOW); + phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_CFG2, cfg2); + + phy_write_mmd_indirect(phydev, DP83867_RGMIICTL, + DP83867_DEVADDR, phydev->addr, 0x0); + + phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL, + DP83867_PHYCTRL_SGMIIEN | + (DP83867_MDI_CROSSOVER_MDIX << + DP83867_MDI_CROSSOVER) | + (FIFO_DEPTH << DP83867_PHYCTRL_RXFIFO_SHIFT) | + (FIFO_DEPTH << DP83867_PHYCTRL_TXFIFO_SHIFT)); + phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_BISCR, 0x0); } if ((phydev->interface >= PHY_INTERFACE_MODE_RGMII_ID) && diff --git a/drivers/net/phy/xilinx_phy.c b/drivers/net/phy/xilinx_phy.c new file mode 100644 index 0000000000..f3eaf2e97c --- /dev/null +++ b/drivers/net/phy/xilinx_phy.c @@ -0,0 +1,144 @@ +/* + * Xilinx PCS/PMA Core phy driver + * + * Copyright (C) 2015 - 2016 Xilinx, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +#include <common.h> +#include <phy.h> +#include <dm.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define MII_PHY_STATUS_SPD_MASK 0x0C00 +#define MII_PHY_STATUS_FULLDUPLEX 0x1000 +#define MII_PHY_STATUS_1000 0x0800 +#define MII_PHY_STATUS_100 0x0400 +#define XPCSPMA_PHY_CTRL_ISOLATE_DISABLE 0xFBFF + +/* Mask used for ID comparisons */ +#define XILINX_PHY_ID_MASK 0xfffffff0 + +/* Known PHY IDs */ +#define XILINX_PHY_ID 0x01740c00 + +/* struct phy_device dev_flags definitions */ +#define XAE_PHY_TYPE_MII 0 +#define XAE_PHY_TYPE_GMII 1 +#define XAE_PHY_TYPE_RGMII_1_3 2 +#define XAE_PHY_TYPE_RGMII_2_0 3 +#define XAE_PHY_TYPE_SGMII 4 +#define XAE_PHY_TYPE_1000BASE_X 5 + +static int xilinxphy_startup(struct phy_device *phydev) +{ + int err; + int status = 0; + + debug("%s\n", __func__); + /* Update the link, but return if there + * was an error + */ + err = genphy_update_link(phydev); + if (err) + return err; + + if (AUTONEG_ENABLE == phydev->autoneg) { + status = phy_read(phydev, MDIO_DEVAD_NONE, MII_LPA); + status = status & MII_PHY_STATUS_SPD_MASK; + + if (status & MII_PHY_STATUS_FULLDUPLEX) + phydev->duplex = DUPLEX_FULL; + else + phydev->duplex = DUPLEX_HALF; + + switch (status) { + case MII_PHY_STATUS_1000: + phydev->speed = SPEED_1000; + break; + + case MII_PHY_STATUS_100: + phydev->speed = SPEED_100; + break; + + default: + phydev->speed = SPEED_10; + break; + } + } else { + int bmcr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); + + if (bmcr < 0) + return bmcr; + + if (bmcr & BMCR_FULLDPLX) + phydev->duplex = DUPLEX_FULL; + else + phydev->duplex = DUPLEX_HALF; + + if (bmcr & BMCR_SPEED1000) + phydev->speed = SPEED_1000; + else if (bmcr & BMCR_SPEED100) + phydev->speed = SPEED_100; + else + phydev->speed = SPEED_10; + } + + /* + * For 1000BASE-X Phy Mode the speed/duplex will always be + * 1000Mbps/fullduplex + */ + if (phydev->flags == XAE_PHY_TYPE_1000BASE_X) { + phydev->duplex = DUPLEX_FULL; + phydev->speed = SPEED_1000; + } + + return 0; +} + +static int xilinxphy_of_init(struct phy_device *phydev) +{ + struct udevice *dev = (struct udevice *)&phydev->dev; + u32 phytype; + + debug("%s\n", __func__); + phytype = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "phy-type", -1); + if (phytype == XAE_PHY_TYPE_1000BASE_X) + phydev->flags |= XAE_PHY_TYPE_1000BASE_X; + + return 0; +} + +static int xilinxphy_config(struct phy_device *phydev) +{ + int temp; + + debug("%s\n", __func__); + xilinxphy_of_init(phydev); + temp = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); + temp &= XPCSPMA_PHY_CTRL_ISOLATE_DISABLE; + phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, temp); + + return 0; +} + +static struct phy_driver xilinxphy_driver = { + .uid = XILINX_PHY_ID, + .mask = XILINX_PHY_ID_MASK, + .name = "Xilinx PCS/PMA PHY", + .features = PHY_GBIT_FEATURES, + .config = &xilinxphy_config, + .startup = &xilinxphy_startup, + .shutdown = &genphy_shutdown, +}; + +int phy_xilinx_init(void) +{ + debug("%s\n", __func__); + phy_register(&xilinxphy_driver); + + return 0; +} diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c index 81274ee13b..5de06ef01e 100644 --- a/drivers/net/xilinx_axi_emac.c +++ b/drivers/net/xilinx_axi_emac.c @@ -251,7 +251,7 @@ static int axiemac_phy_init(struct udevice *dev) } /* Interface - look at tsec */ - phydev = phy_connect(priv->bus, priv->phyaddr, dev, 0); + phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface); phydev->supported &= supported; phydev->advertising = phydev->supported; @@ -264,11 +264,29 @@ static int axiemac_phy_init(struct udevice *dev) /* Setting axi emac and phy to proper setting */ static int setup_phy(struct udevice *dev) { - u32 speed, emmc_reg; + u16 temp; + u32 speed, emmc_reg, ret; struct axidma_priv *priv = dev_get_priv(dev); struct axi_regs *regs = priv->iobase; struct phy_device *phydev = priv->phydev; + if (priv->interface == PHY_INTERFACE_MODE_SGMII) { + /* + * In SGMII cases the isolate bit might set + * after DMA and ethernet resets and hence + * check and clear if set. + */ + ret = phyread(priv, priv->phyaddr, MII_BMCR, &temp); + if (ret) + return 0; + if (temp & BMCR_ISOLATE) { + temp &= ~BMCR_ISOLATE; + ret = phywrite(priv, priv->phyaddr, MII_BMCR, temp); + if (ret) + return 0; + } + } + if (phy_startup(phydev)) { printf("axiemac: could not initialize PHY %s\n", phydev->dev->name); @@ -697,7 +715,7 @@ static int axi_emac_ofdata_to_platdata(struct udevice *dev) if (phy_mode) pdata->phy_interface = phy_get_interface_by_name(phy_mode); if (pdata->phy_interface == -1) { - debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); + printf("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); return -EINVAL; } priv->interface = pdata->phy_interface; diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index b3821c31a9..aec8077f10 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -57,6 +57,8 @@ DECLARE_GLOBAL_DATA_PTR; #define ZYNQ_GEM_NWCFG_SPEED1000 0x000000400 /* 1Gbps operation */ #define ZYNQ_GEM_NWCFG_FDEN 0x000000002 /* Full Duplex mode */ #define ZYNQ_GEM_NWCFG_FSREM 0x000020000 /* FCS removal */ +#define ZYNQ_GEM_NWCFG_SGMII_ENBL 0x080000000 /* SGMII Enable */ +#define ZYNQ_GEM_NWCFG_PCS_SEL 0x000000800 /* PCS select */ #ifdef CONFIG_ARM64 #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000100000 /* Div pclk by 64, max 160MHz */ #else @@ -91,6 +93,8 @@ DECLARE_GLOBAL_DATA_PTR; #define ZYNQ_GEM_TSR_DONE 0x00000020 /* Tx done mask */ +#define ZYNQ_GEM_PCS_CTL_ANEG_ENBL 0x1000 + /* Use MII register 1 (MII status register) to detect PHY */ #define PHY_DETECT_REG 1 @@ -137,7 +141,9 @@ struct zynq_gem_regs { u32 reserved6[18]; #define STAT_SIZE 44 u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */ - u32 reserved7[164]; + u32 reserved9[20]; + u32 pcscntrl; + u32 reserved7[143]; u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */ u32 reserved8[15]; u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */ @@ -330,10 +336,12 @@ static int zynq_phy_init(struct udevice *dev) /* Enable only MDIO bus */ writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, ®s->nwctrl); - ret = phy_detection(dev); - if (ret) { - printf("GEM PHY init failed\n"); - return ret; + if (priv->interface != PHY_INTERFACE_MODE_SGMII) { + ret = phy_detection(dev); + if (ret) { + printf("GEM PHY init failed\n"); + return ret; + } } priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev, @@ -351,7 +359,7 @@ static int zynq_phy_init(struct udevice *dev) static int zynq_gem_init(struct udevice *dev) { - u32 i; + u32 i, nwconfig; unsigned long clk_rate = 0; struct zynq_gem_priv *priv = dev_get_priv(dev); struct zynq_gem_regs *regs = priv->iobase; @@ -426,14 +434,25 @@ static int zynq_gem_init(struct udevice *dev) return -1; } + nwconfig = ZYNQ_GEM_NWCFG_INIT; + + if (priv->interface == PHY_INTERFACE_MODE_SGMII) { + nwconfig |= ZYNQ_GEM_NWCFG_SGMII_ENBL | + ZYNQ_GEM_NWCFG_PCS_SEL; +#ifdef CONFIG_ARM64 + writel(readl(®s->pcscntrl) | ZYNQ_GEM_PCS_CTL_ANEG_ENBL, + ®s->pcscntrl); +#endif + } + switch (priv->phydev->speed) { case SPEED_1000: - writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED1000, + writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED1000, ®s->nwcfg); clk_rate = ZYNQ_GEM_FREQUENCY_1000; break; case SPEED_100: - writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED100, + writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED100, ®s->nwcfg); clk_rate = ZYNQ_GEM_FREQUENCY_100; break; @@ -561,6 +580,23 @@ static void zynq_gem_halt(struct udevice *dev) ZYNQ_GEM_NWCTRL_TXEN_MASK, 0); } +__weak int zynq_board_read_rom_ethaddr(unsigned char *ethaddr) +{ + return -ENOSYS; +} + +static int zynq_gem_read_rom_mac(struct udevice *dev) +{ + int retval; + struct eth_pdata *pdata = dev_get_platdata(dev); + + retval = zynq_board_read_rom_ethaddr(pdata->enetaddr); + if (retval == -ENOSYS) + retval = 0; + + return retval; +} + static int zynq_gem_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg) { @@ -611,9 +647,7 @@ static int zynq_gem_probe(struct udevice *dev) if (ret) return ret; - zynq_phy_init(dev); - - return 0; + return zynq_phy_init(dev); } static int zynq_gem_remove(struct udevice *dev) @@ -634,6 +668,7 @@ static const struct eth_ops zynq_gem_ops = { .free_pkt = zynq_gem_free_pkt, .stop = zynq_gem_halt, .write_hwaddr = zynq_gem_setup_mac, + .read_rom_hwaddr = zynq_gem_read_rom_mac, }; static int zynq_gem_ofdata_to_platdata(struct udevice *dev) @@ -663,6 +698,8 @@ static int zynq_gem_ofdata_to_platdata(struct udevice *dev) } priv->interface = pdata->phy_interface; + priv->emio = fdtdec_get_bool(gd->fdt_blob, dev->of_offset, "xlnx,emio"); + printf("ZYNQ GEM: %lx, phyaddr %d, interface %s\n", (ulong)priv->iobase, priv->phyaddr, phy_string_for_interface(priv->interface)); diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index 27668f2a89..09bfabcfdf 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -47,18 +47,6 @@ #endif #define CONFIG_BOARD_LATE_INIT -/* interrupt controller */ -#ifdef XILINX_INTC_BASEADDR -# define CONFIG_SYS_INTC_0_ADDR XILINX_INTC_BASEADDR -# define CONFIG_SYS_INTC_0_NUM XILINX_INTC_NUM_INTR_INPUTS -#endif - -/* timer */ -#if defined(XILINX_TIMER_BASEADDR) && defined(XILINX_TIMER_IRQ) -# define CONFIG_SYS_TIMER_0_ADDR XILINX_TIMER_BASEADDR -# define CONFIG_SYS_TIMER_0_IRQ XILINX_TIMER_IRQ -#endif - /* watchdog */ #if defined(XILINX_WATCHDOG_BASEADDR) && defined(XILINX_WATCHDOG_IRQ) # define CONFIG_WATCHDOG_BASEADDR XILINX_WATCHDOG_BASEADDR diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 4e066cdfd2..8cea61080d 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -26,8 +26,11 @@ #define CONFIG_SYS_ALT_MEMTEST #define CONFIG_SYS_MEMTEST_SCRATCH 0xfffc0000 -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_SDRAM_SIZE +#ifndef CONFIG_NR_DRAM_BANKS +# define CONFIG_NR_DRAM_BANKS 2 +#endif +#define CONFIG_SYS_MEMTEST_START 0 +#define CONFIG_SYS_MEMTEST_END 1000 /* Have release address at the end of 256MB for now */ #define CPU_RELEASE_ADDR 0xFFFFFF0 @@ -39,7 +42,7 @@ # define CONFIG_IDENT_STRING " Xilinx ZynqMP" #endif -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE /* Flat Device Tree Definitions */ @@ -68,6 +71,7 @@ #define CONFIG_CMD_FAT #define CONFIG_CMD_FS_GENERIC #define CONFIG_DOS_PARTITION +#define CONFIG_EFI_PARTITION #define CONFIG_MP #define CONFIG_CMD_MII @@ -93,6 +97,9 @@ # ifndef CONFIG_ZYNQ_SDHCI_MAX_FREQ # define CONFIG_ZYNQ_SDHCI_MAX_FREQ 200000000 # endif +#endif + +#if defined(CONFIG_ZYNQ_SDHCI) || defined(CONFIG_ZYNQMP_USB) # define CONFIG_FAT_WRITE # define CONFIG_CMD_EXT4_WRITE #endif @@ -168,7 +175,7 @@ #define CONFIG_PREBOOT "run bootargs" #define CONFIG_BOOTCOMMAND "run $modeboot" -#define CONFIG_BOOTDELAY 5 +#define CONFIG_BOOTDELAY 3 #define CONFIG_BOARD_LATE_INIT @@ -181,7 +188,6 @@ #define CONFIG_SYS_CBSIZE 2048 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE #define CONFIG_SYS_LONGHELP #define CONFIG_CMDLINE_EDITING @@ -221,7 +227,7 @@ #define CONFIG_LIBATA #define CONFIG_SCSI_AHCI #define CONFIG_SCSI_AHCI_PLAT -#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 #define CONFIG_SYS_SCSI_MAX_LUN 1 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ CONFIG_SYS_SCSI_MAX_LUN) diff --git a/include/configs/xilinx_zynqmp_ep.h b/include/configs/xilinx_zynqmp_ep.h index 337312e58c..aa58b62531 100644 --- a/include/configs/xilinx_zynqmp_ep.h +++ b/include/configs/xilinx_zynqmp_ep.h @@ -22,11 +22,6 @@ #define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR, \ ZYNQMP_USB1_XHCI_BASEADDR} -/* Physical Memory Map */ -#define CONFIG_NR_DRAM_BANKS 1 -#define CONFIG_SYS_SDRAM_BASE 0 -#define CONFIG_SYS_SDRAM_SIZE 0x40000000 - #define COUNTER_FREQUENCY 4000000 #include <configs/xilinx_zynqmp.h> diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index c2ed28af14..d8e3fa4e5a 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -47,6 +47,7 @@ # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN # define CONFIG_PHY_MARVELL # define CONFIG_PHY_REALTEK +# define CONFIG_PHY_XILINX # define CONFIG_BOOTP_SERVERIP # define CONFIG_BOOTP_BOOTPATH # define CONFIG_BOOTP_GATEWAY @@ -202,7 +203,11 @@ # define CONFIG_ENV_OFFSET 0xE0000 #endif +/* enable preboot to be loaded before CONFIG_BOOTDELAY */ +#define CONFIG_PREBOOT + /* Default environment */ +#ifndef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ "fit_image=fit.itb\0" \ "load_addr=0x2000000\0" \ @@ -211,6 +216,29 @@ "nor_flash_off=0xE2100000\0" \ "fdt_high=0x20000000\0" \ "initrd_high=0x20000000\0" \ + "loadbootenv_addr=0x2000000\0" \ + "bootenv=uEnv.txt\0" \ + "bootenv_dev=mmc\0" \ + "loadbootenv=load ${bootenv_dev} 0 ${loadbootenv_addr} ${bootenv}\0" \ + "importbootenv=echo Importing environment from ${bootenv_dev} ...; " \ + "env import -t ${loadbootenv_addr} $filesize\0" \ + "bootenv_existence_test=test -e ${bootenv_dev} 0 /${bootenv}\0" \ + "setbootenv=if env run bootenv_existence_test; then " \ + "if env run loadbootenv; then " \ + "env run importbootenv; " \ + "fi; " \ + "fi; \0" \ + "sd_loadbootenv=set bootenv_dev mmc && " \ + "run setbootenv \0" \ + "usb_loadbootenv=set bootenv_dev usb && usb start && run setbootenv \0" \ + "preboot=if test $modeboot = sdboot; then " \ + "run sd_loadbootenv; " \ + "echo Checking if uenvcmd is set ...; " \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...; " \ + "run uenvcmd; " \ + "fi; " \ + "fi; \0" \ "norboot=echo Copying FIT from NOR flash to RAM... && " \ "cp.b ${nor_flash_off} ${load_addr} ${fit_size} && " \ "bootm ${load_addr}\0" \ @@ -225,6 +253,7 @@ "load usb 0 ${load_addr} ${fit_image} && " \ "bootm ${load_addr}; fi\0" \ DFU_ALT_INFO +#endif #define CONFIG_BOOTCOMMAND "run $modeboot" #define CONFIG_BOOTDELAY 3 /* -1 to Disable autoboot */ diff --git a/include/configs/zynq_zybo.h b/include/configs/zynq_zybo.h index 0882fe36bd..637b1c5ffe 100644 --- a/include/configs/zynq_zybo.h +++ b/include/configs/zynq_zybo.h @@ -17,6 +17,9 @@ #define CONFIG_ZYNQ_I2C0 #define CONFIG_ZYNQ_I2C1 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_CMD_EEPROM +#define CONFIG_ZYNQ_GEM_EEPROM_ADDR 0x50 +#define CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET 0xFA #define CONFIG_DISPLAY #define CONFIG_I2C_EDID diff --git a/include/phy.h b/include/phy.h index 09bbe483a4..21459a8c80 100644 --- a/include/phy.h +++ b/include/phy.h @@ -264,6 +264,7 @@ int phy_smsc_init(void); int phy_teranetics_init(void); int phy_ti_init(void); int phy_vitesse_init(void); +int phy_xilinx_init(void); int board_phy_config(struct phy_device *phydev); int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id); |
