diff options
43 files changed, 4 insertions, 4874 deletions
diff --git a/board/amcc/ebony/Kconfig b/board/amcc/ebony/Kconfig deleted file mode 100644 index ba73148f7f..0000000000 --- a/board/amcc/ebony/Kconfig +++ /dev/null @@ -1,16 +0,0 @@ -if TARGET_EBONY - -config SYS_BOARD - default "ebony" - -config SYS_VENDOR - default "amcc" - -config SYS_CONFIG_NAME - default "ebony" - -config DISPLAY_BOARDINFO - bool - default y - -endif diff --git a/board/amcc/ebony/MAINTAINERS b/board/amcc/ebony/MAINTAINERS deleted file mode 100644 index bc62851509..0000000000 --- a/board/amcc/ebony/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -EBONY BOARD -M: Stefan Roese <sr@denx.de> -S: Maintained -F: board/amcc/ebony/ -F: include/configs/ebony.h -F: configs/ebony_defconfig diff --git a/board/amcc/ebony/Makefile b/board/amcc/ebony/Makefile deleted file mode 100644 index 5876486f58..0000000000 --- a/board/amcc/ebony/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2002-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = ebony.o flash.o -extra-y += init.o diff --git a/board/amcc/ebony/README b/board/amcc/ebony/README deleted file mode 100644 index 4df00b3561..0000000000 --- a/board/amcc/ebony/README +++ /dev/null @@ -1,136 +0,0 @@ - AMCC Ebony Board - - Last Update: September 12, 2002 -======================================================================= - -This file contains some handy info regarding U-Boot and the AMCC -Ebony evaluation board. See the README.ppc440 for additional -information. - - -SWITCH SETTINGS & JUMPERS -========================== - -Here's what I've been using successfully. If you feel inclined to -change things ... please read the docs! - -DIPSW U46 U80 ------------------------- -SW 1 off on -SW 2 on on -SW 3 on on -SW 4 off on -SW 5 on off -SW 6 on on -SW 7 on off -SW 8 on off - -J41: strapped -J42: open - -All others are factory default. - - -I2C probe -===================== - -The i2c utilities have been tested on both Rev B. and Rev C. and -look good. The CONFIG_SYS_I2C_NOPROBES macro is defined to prevent -probing the CDCV850 clock controller at address 0x69 (since reading -it causes the i2c implementation to misbehave. The output of -'i2c probe' should look like this (assuming you are only using a single -SO-DIMM: - -=> i2c probe -Valid chip addresses: 50 53 54 -Excluded chip addresses: 69 - - -GETTING OUT OF I2C TROUBLE -=========================== - -If you're like me ... you may have screwed up your bootstrap serial -eeprom ... or worse, your SPD eeprom when experimenting with the -i2c commands. If so, here are some ideas on how to get out of -trouble: - -Serial bootstrap eeprom corruption: ------------------------------------ -Power down the board and set the following straps: - -J41 - open -J42 - strapped - -This will select the default sys0 and sys1 settings (the serial -eeproms are not used). Then power up the board and fix the serial -eeprom using the 'i2c mm' command. Here are the values I currently -use: - -=> i2c md 50 0 10 -0000: bf a2 04 01 ae 94 11 00 00 00 00 00 00 00 00 00 ................ - -=> i2c md 54 0 10 -0000: 8f b3 24 01 4d 14 11 00 00 00 00 00 00 00 00 00 ..$.M........... - -Once you have the eeproms set correctly change the -J41/J42 straps as you desire. - -SPD eeprom corruption: ------------------------- -I've corrupted the SPD eeprom several times ... perhaps too much coffee -and not enough presence of mind ;-). By default, the ebony code uses -the SPD to initialize the DDR SDRAM control registers. So if the SPD -eeprom is corrupted, U-Boot will never get into ram. Here's how I got -out of this situation: - -0. First, _before_ playing with the i2c utilities, do an 'i2c probe', then -use 'i2c md' to capture the various device contents to a file. Some day -you may be glad you did this ... trust me :-). Otherwise try the -following: - -1. In the include/configs/EBONY.h file find the line that defines -the CONFIG_SPD_EEPROM macro and undefine it. E.g: - -#undef CONFIG_SPD_EEPROM - -This will make the code use default SDRAM control register -settings without using the SPD eeprom. - -2. Rebuild U-Boot - -3. Load the new U-Boot image and reboot ebony. - -4. Repair the SPD eeprom using the 'i2c mm' command. Here's the eeprom -contents that work with the default SO-DIMM that comes with the -ebony board (micron 8VDDT164AG-265A1). Note: these are probably -_not_ the factory settings ... but they work. - -=> i2c md 53 0 10 80 -0000: 80 08 07 0c 0a 01 40 00 04 75 75 00 80 08 00 01 ......@..uu..... -0010: 0e 04 0c 01 02 20 00 a0 75 00 00 50 3c 50 2d 20 ..... ..u..P<P- -0020: 90 90 50 50 00 00 00 00 00 41 4b 34 32 75 00 00 ..PP.....AK42u.. -0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 9c ................ -0040: 2c 00 00 00 00 00 00 00 08 38 56 44 44 54 31 36 ,........8VDDT16 -0050: 36 34 41 47 2d 32 36 35 41 31 20 01 00 01 2c 63 64AG-265A1 ...,c -0060: 22 25 ab 00 00 00 00 00 00 00 00 00 00 00 00 00 "%.............. -0070: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ - - -PCI DOUBLE-ENUMERATION WOES -=========================== - -If you're not using PCI-X cards and are simply using 32-bit and/or -33 MHz cards via extenders and the like, you may notice that the -initial pci scan reports various devices twice ... and configuration -does not succeed (one or more devices are enumerated twice). To correct -this we replaced the 2K ohm resistor on the IDSEL line(s) with a -22 ohm resistor and the problem went away. This change hasn't broken -anything yet -- use at your own risk. - -We never tested anything other than 33 MHz/32-bit cards. If you have -the chance to do this, please let me know how things turn out :-) - - -Regards, ---Scott -<smcnutt@artesyncp.com> diff --git a/board/amcc/ebony/config.mk b/board/amcc/ebony/config.mk deleted file mode 100644 index f18b09710d..0000000000 --- a/board/amcc/ebony/config.mk +++ /dev/null @@ -1,16 +0,0 @@ -# -# (C) Copyright 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 -endif diff --git a/board/amcc/ebony/ebony.c b/board/amcc/ebony/ebony.c deleted file mode 100644 index eb424489ef..0000000000 --- a/board/amcc/ebony/ebony.c +++ /dev/null @@ -1,151 +0,0 @@ -/* - * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/processor.h> -#include <spd_sdram.h> - -#define BOOT_SMALL_FLASH 32 /* 00100000 */ -#define FLASH_ONBD_N 2 /* 00000010 */ -#define FLASH_SRAM_SEL 1 /* 00000001 */ - -DECLARE_GLOBAL_DATA_PTR; - -long int fixed_sdram(void); - -int board_early_init_f(void) -{ - uint reg; - unsigned char *fpga_base = (unsigned char *)CONFIG_SYS_FPGA_BASE; - unsigned char status; - - /*-------------------------------------------------------------------- - * Setup the external bus controller/chip selects - *-------------------------------------------------------------------*/ - mtdcr(EBC0_CFGADDR, EBC0_CFG); - reg = mfdcr(EBC0_CFGDATA); - mtdcr(EBC0_CFGDATA, reg | 0x04000000); /* Set ATC */ - - mtebc(PB1AP, 0x02815480); /* NVRAM/RTC */ - mtebc(PB1CR, 0x48018000); /* BA=0x480 1MB R/W 8-bit */ - mtebc(PB7AP, 0x01015280); /* FPGA registers */ - mtebc(PB7CR, 0x48318000); /* BA=0x483 1MB R/W 8-bit */ - - /* read FPGA_REG0 and set the bus controller */ - status = *fpga_base; - if ((status & BOOT_SMALL_FLASH) && !(status & FLASH_ONBD_N)) { - mtebc(PB0AP, 0x9b015480); /* FLASH/SRAM */ - mtebc(PB0CR, 0xfff18000); /* BAS=0xfff 1MB R/W 8-bit */ - mtebc(PB2AP, 0x9b015480); /* 4MB FLASH */ - mtebc(PB2CR, 0xff858000); /* BAS=0xff8 4MB R/W 8-bit */ - } else { - mtebc(PB0AP, 0x9b015480); /* 4MB FLASH */ - mtebc(PB0CR, 0xffc58000); /* BAS=0xffc 4MB R/W 8-bit */ - - /* set CS2 if FLASH_ONBD_N == 0 */ - if (!(status & FLASH_ONBD_N)) { - mtebc(PB2AP, 0x9b015480); /* FLASH/SRAM */ - mtebc(PB2CR, 0xff818000); /* BAS=0xff8 4MB R/W 8-bit */ - } - } - - /*-------------------------------------------------------------------- - * Setup the interrupt controller polarities, triggers, etc. - *-------------------------------------------------------------------*/ - mtdcr(UIC0SR, 0xffffffff); /* clear all */ - mtdcr(UIC0ER, 0x00000000); /* disable all */ - mtdcr(UIC0CR, 0x00000009); /* SMI & UIC1 crit are critical */ - mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */ - mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */ - mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(UIC0SR, 0xffffffff); /* clear all */ - - mtdcr(UIC1SR, 0xffffffff); /* clear all */ - mtdcr(UIC1ER, 0x00000000); /* disable all */ - mtdcr(UIC1CR, 0x00000000); /* all non-critical */ - mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */ - mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */ - mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(UIC1SR, 0xffffffff); /* clear all */ - - return 0; -} - -int checkboard(void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - printf("Board: Ebony - AMCC PPC440GP Evaluation Board"); - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc('\n'); - - return (0); -} - -phys_size_t initdram(int board_type) -{ - long dram_size = 0; - -#if defined(CONFIG_SPD_EEPROM) - dram_size = spd_sdram(); -#else - dram_size = fixed_sdram(); -#endif - return dram_size; -} - -#if !defined(CONFIG_SPD_EEPROM) -/************************************************************************* - * fixed sdram init -- doesn't use serial presence detect. - * - * Assumes: 128 MB, non-ECC, non-registered - * PLB @ 133 MHz - * - ************************************************************************/ -long int fixed_sdram(void) -{ - uint reg; - - /*-------------------------------------------------------------------- - * Setup some default - *------------------------------------------------------------------*/ - mtsdram(SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */ - mtsdram(SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ - mtsdram(SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */ - mtsdram(SDRAM0_WDDCTR, 0x00000000); /* wrcp=0 dcd=0 */ - mtsdram(SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */ - - /*-------------------------------------------------------------------- - * Setup for board-specific specific mem - *------------------------------------------------------------------*/ - /* - * Following for CAS Latency = 2.5 @ 133 MHz PLB - */ - mtsdram(SDRAM0_B0CR, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */ - mtsdram(SDRAM0_TR0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */ - /* RA=10 RD=3 */ - mtsdram(SDRAM0_TR1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */ - mtsdram(SDRAM0_RTR, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */ - mtsdram(SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM */ - udelay(400); /* Delay 200 usecs (min) */ - - /*-------------------------------------------------------------------- - * Enable the controller, then wait for DCEN to complete - *------------------------------------------------------------------*/ - mtsdram(SDRAM0_CFG0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */ - for (;;) { - mfsdram(SDRAM0_MCSTS, reg); - if (reg & 0x80000000) - break; - } - - return (128 * 1024 * 1024); /* 128 MB */ -} -#endif /* !defined(CONFIG_SPD_EEPROM) */ diff --git a/board/amcc/ebony/flash.c b/board/amcc/ebony/flash.c deleted file mode 100644 index 5740a5623b..0000000000 --- a/board/amcc/ebony/flash.c +++ /dev/null @@ -1,155 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2002 Jun Gu <jung@artesyncp.com> - * Add support for Am29F016D and dynamic switch setting. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Modified 4/5/2001 - * Wait for completion of each sector erase command issued - * 4/5/2001 - * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com - */ - -#include <common.h> -#include <asm/ppc4xx.h> -#include <asm/processor.h> -#include <asm/io.h> - -#undef DEBUG -#ifdef DEBUG -#define DEBUGF(x...) printf(x) -#else -#define DEBUGF(x...) -#endif /* DEBUG */ - -#define BOOT_SMALL_FLASH 32 /* 00100000 */ -#define FLASH_ONBD_N 2 /* 00000010 */ -#define FLASH_SRAM_SEL 1 /* 00000001 */ - -#define BOOT_SMALL_FLASH_VAL 4 -#define FLASH_ONBD_N_VAL 2 -#define FLASH_SRAM_SEL_VAL 1 - -static unsigned long flash_addr_table[8][CONFIG_SYS_MAX_FLASH_BANKS] = { - {0xffc00000, 0xffe00000, 0xff880000}, /* 0:000: configuraton 3 */ - {0xffc00000, 0xffe00000, 0xff800000}, /* 1:001: configuraton 4 */ - {0xffc00000, 0xffe00000, 0x00000000}, /* 2:010: configuraton 7 */ - {0xffc00000, 0xffe00000, 0x00000000}, /* 3:011: configuraton 8 */ - {0xff800000, 0xffa00000, 0xfff80000}, /* 4:100: configuraton 1 */ - {0xff800000, 0xffa00000, 0xfff00000}, /* 5:101: configuraton 2 */ - {0xffc00000, 0xffe00000, 0x00000000}, /* 6:110: configuraton 5 */ - {0xffc00000, 0xffe00000, 0x00000000} /* 7:111: configuraton 6 */ -}; - -/* - * include common flash code (for amcc boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(vu_long * addr, flash_info_t * info); - -/* - * Override the weak default mapping function with a board specific one - */ -u32 flash_get_bank_size(int cs, int idx) -{ - u8 reg = in_8((void *)CONFIG_SYS_FPGA_BASE); - - if ((reg & BOOT_SMALL_FLASH) && !(reg & FLASH_ONBD_N)) { - /* - * cs0: small flash (512KiB) - * cs2: 2 * big flash (2 * 2MiB) - */ - if (cs == 0) - return flash_info[2].size; - if (cs == 2) - return flash_info[0].size + flash_info[1].size; - } else { - /* - * cs0: 2 * big flash (2 * 2MiB) - * cs2: small flash (512KiB) - */ - if (cs == 0) - return flash_info[0].size + flash_info[1].size; - if (cs == 2) - return flash_info[2].size; - } - - return 0; -} - -unsigned long flash_init(void) -{ - unsigned long total_b = 0; - unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS]; - unsigned char *fpga_base = (unsigned char *)CONFIG_SYS_FPGA_BASE; - unsigned char switch_status; - unsigned short index = 0; - int i; - - /* read FPGA base register FPGA_REG0 */ - switch_status = *fpga_base; - - /* check the bitmap of switch status */ - if (switch_status & BOOT_SMALL_FLASH) { - index += BOOT_SMALL_FLASH_VAL; - } - if (switch_status & FLASH_ONBD_N) { - index += FLASH_ONBD_N_VAL; - } - if (switch_status & FLASH_SRAM_SEL) { - index += FLASH_SRAM_SEL_VAL; - } - - DEBUGF("\n"); - DEBUGF("FLASH: Index: %d\n", index); - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - flash_info[i].sector_count = -1; - flash_info[i].size = 0; - - /* check whether the address is 0 */ - if (flash_addr_table[index][i] == 0) { - continue; - } - - /* call flash_get_size() to initialize sector address */ - size_b[i] = flash_get_size((vu_long *) - flash_addr_table[index][i], - &flash_info[i]); - flash_info[i].size = size_b[i]; - if (flash_info[i].flash_id == FLASH_UNKNOWN) { - printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", - i, size_b[i], size_b[i] << 20); - flash_info[i].sector_count = -1; - flash_info[i].size = 0; - } - - /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1, - &flash_info[2]); -#ifdef CONFIG_ENV_IS_IN_FLASH - (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[2]); - (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND, - CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[2]); -#endif - - total_b += flash_info[i].size; - } - - return total_b; -} diff --git a/board/amcc/ebony/init.S b/board/amcc/ebony/init.S deleted file mode 100644 index 904e648987..0000000000 --- a/board/amcc/ebony/init.S +++ /dev/null @@ -1,41 +0,0 @@ -/* -* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com> - * SPDX-License-Identifier: GPL-2.0+ -*/ - -#include <ppc_asm.tmpl> -#include <config.h> -#include <asm/mmu.h> -#include <asm/ppc4xx.h> - -/************************************************************************** - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - * - *************************************************************************/ - - .section .bootpg,"ax" - .globl tlbtab - -tlbtab: - tlbtab_start - - tlbentry(0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG) - - /* - * TLB entries for SDRAM are not needed on this platform. - * They are dynamically generated in the SPD DDR(2) detection - * routine. - */ - - tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_RWX) - tlbentry(CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_RWX) - tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG) - tlbtab_end diff --git a/board/amcc/ocotea/Kconfig b/board/amcc/ocotea/Kconfig deleted file mode 100644 index 489e8a4da3..0000000000 --- a/board/amcc/ocotea/Kconfig +++ /dev/null @@ -1,16 +0,0 @@ -if TARGET_OCOTEA - -config SYS_BOARD - default "ocotea" - -config SYS_VENDOR - default "amcc" - -config SYS_CONFIG_NAME - default "ocotea" - -config DISPLAY_BOARDINFO - bool - default y - -endif diff --git a/board/amcc/ocotea/MAINTAINERS b/board/amcc/ocotea/MAINTAINERS deleted file mode 100644 index 34634a2f77..0000000000 --- a/board/amcc/ocotea/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -OCOTEA BOARD -M: Stefan Roese <sr@denx.de> -S: Maintained -F: board/amcc/ocotea/ -F: include/configs/ocotea.h -F: configs/ocotea_defconfig diff --git a/board/amcc/ocotea/Makefile b/board/amcc/ocotea/Makefile deleted file mode 100644 index 7646bbb961..0000000000 --- a/board/amcc/ocotea/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2002-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = ocotea.o flash.o -extra-y += init.o diff --git a/board/amcc/ocotea/README.ocotea b/board/amcc/ocotea/README.ocotea deleted file mode 100644 index be79b03c8a..0000000000 --- a/board/amcc/ocotea/README.ocotea +++ /dev/null @@ -1,73 +0,0 @@ - AMCC Ocotea Board - - Last Update: March 2, 2004 -======================================================================= - -This file contains some handy info regarding U-Boot and the AMCC -Ocotea 440gx evaluation board. See the README.ppc440 for additional -information. - - -SWITCH SETTINGS & JUMPERS -========================== - -Here's what I've been using successfully. If you feel inclined to -change things ... please read the docs! - -DIPSW U46 U80 ------------------------- -SW 1 off off -SW 2 on off -SW 3 off off -SW 4 off off -SW 5 off off -SW 6 on on -SW 7 on off -SW 8 on off - -J41: strapped -J42: open - -All others are factory default. - - -I2C Information -===================== - -See README.ebony for information. - -PCI -=========================== - -Untested at the time of writing. - -PPC440GX Ethernet EMACs -=========================== - -All EMAC ports have been tested and are known to work -with EPS Group 4. - -Special note about the Cicada CIS8201: - The CIS8201 Gigabit PHY comes up in GMII mode by default. - One must hit an extended register to allow use of RGMII mode. - This has been done in the 440gx_enet.c file with a #ifdef/endif - pair. - -AMCC does not store the EMAC ethernet addresses within their PIBS bootloader. -The addresses contained in the config header file are from my particular -board and you _*should*_ change them to reflect your board either in the -config file and/or in your environment variables. I found the addresses on -labels on the bottom side of the board. - - -BDI2k or JTAG Debugging -=========================== - -For ease of debugging you can swap the small boot flash and external SRAM -by changing U46:3 to on. You can then use the sram as your boot flash by -loading the sram via the jtag debugger. - - -Regards, ---Travis -<tsawyer@sandburst.com> diff --git a/board/amcc/ocotea/README.ocotea-PIBS-to-U-Boot b/board/amcc/ocotea/README.ocotea-PIBS-to-U-Boot deleted file mode 100644 index 25dd2a2378..0000000000 --- a/board/amcc/ocotea/README.ocotea-PIBS-to-U-Boot +++ /dev/null @@ -1,99 +0,0 @@ ------------------------------------------- -Installation of U-Boot using PIBS firmware ------------------------------------------- - -This document describes how to install U-Boot on the Ocotea PPC440GX -Evaluation Board. We do not erase the PIBS firmware but install U-Boot in the -soldered FLASH. After this you should be able to switch between PIBS and -U-Boot via the switch U46 SW1. Please check that SW1 is off (= open) before -continuing. - -Connect to the serial port 0 (J11 lower) of the Ocotea board using the cu -program. See the hints for configuring cu above. Make sure you can -communicate with the PIBS firmware: reset the board and hit ENTER a couple of -times until you see the PIBS prompt (PIBS $). Then proceed as follows: - - -Read MAC Addresses from PIBS ----------------------------- - -To read the configured MAC addresses available on your Ocotea board please use -the following commands: - -PIBS $ echo $hwdaddr0 -000173017FE3 -PIBS $ echo $hwdaddr1 -000173017FE4 -PIBS $ echo $hwdaddr2 -000173017FE1 -PIBS $ echo $hwdaddr3 -000173017FE2 - -In U-Boot this is stored in the following environment variables: - -* Ethernet Address 0: ethaddr = 000173017FE3 (==> 00:01:73:01:7F:E3) -* Ethernet Address 1: eth1addr = 000173017FE4 (==> 00:01:73:01:7F:E4) -* Ethernet Address 2: eth2addr = 000173017FE1 (==> 00:01:73:01:7F:E1) -* Ethernet Address 3: eth3addr = 000173017FE2 (==> 00:01:73:01:7F:E2) - - -Configure the network interface (ent0 == emac0) ------------------------------------------------ - -To download the U-Boot image we need to configure the ethernet interface with -the following commands: - -PIBS $ ifconfig ent0 192.168.160.142 netmask 255.255.0.0 up -PIBS $ set ipdstaddr0=192.168.1.1 -status: writing PIBS variable value to FLASH -PIBS $ set bootfilename=/tftpboot/ocotea/u-boot.bin -status: writing PIBS variable value to FLASH - -Please insert correct parameters for your configuration (ip-addresses and -file-location). - - -Program U-Boot into soldered User-FLASH ---------------------------------------- - -Please make sure to use a newer version of U-Boot (at least 1.1.3), since -older versions don't support running from user-FLASH. - -To program U-Boot into the soldered user-FLASH use the following command: - -PIBS $ storefile bin eth 0xffbc0000 - -This commands loads the file vis ethernet into ram and copies it into the -user-FLASH. - - -Switch to U-Boot ----------------- - -Now you can turn your board off and switch SW1 (U46) to on (= closed). After -powering the board you should see the following message: - -U-Boot 1.1.3 (Apr 5 2005 - 22:59:57) - -AMCC PowerPC 440 GX Rev. C -Board: AMCC 440GX Evaluation Board - VCO: 1066 MHz - CPU: 533 MHz - PLB: 152 MHz - OPB: 76 MHz - EPB: 76 MHz -I2C: ready -DRAM: 256 MB -FLASH: 5 MB -PCI: Bus Dev VenId DevId Class Int -In: serial -Out: serial -Err: serial -KGDB: kgdb ready -ready -Net: ppc_440x_eth0, ppc_440x_eth1, ppc_440x_eth2, ppc_440x_eth3 -BEDBUG:ready -=> - - -April 06 2005, Stefan Roese <sr@denx.de> diff --git a/board/amcc/ocotea/config.mk b/board/amcc/ocotea/config.mk deleted file mode 100644 index e19b561f9e..0000000000 --- a/board/amcc/ocotea/config.mk +++ /dev/null @@ -1,20 +0,0 @@ -# -# (C) Copyright 2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# -# AMCC 440GX Reference Platform (Ocotea) board -# - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 -endif diff --git a/board/amcc/ocotea/flash.c b/board/amcc/ocotea/flash.c deleted file mode 100644 index a9bbf045d4..0000000000 --- a/board/amcc/ocotea/flash.c +++ /dev/null @@ -1,134 +0,0 @@ -/* - * (C) Copyright 2004-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2002 Jun Gu <jung@artesyncp.com> - * Add support for Am29F016D and dynamic switch setting. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Modified 4/5/2001 - * Wait for completion of each sector erase command issued - * 4/5/2001 - * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com - */ - -#include <common.h> -#include <asm/ppc4xx.h> -#include <asm/processor.h> - -#undef DEBUG - -#ifdef DEBUG -#define DEBUGF(x...) printf(x) -#else -#define DEBUGF(x...) -#endif /* DEBUG */ - -#define BOOT_SMALL_FLASH 0x40 /* 01000000 */ -#define FLASH_ONBD_N 2 /* 00000010 */ -#define FLASH_SRAM_SEL 1 /* 00000001 */ -#define FLASH_ONBD_N 2 /* 00000010 */ -#define FLASH_SRAM_SEL 1 /* 00000001 */ - -#define BOOT_SMALL_FLASH_VAL 4 -#define FLASH_ONBD_N_VAL 2 -#define FLASH_SRAM_SEL_VAL 1 - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -static unsigned long flash_addr_table[8][CONFIG_SYS_MAX_FLASH_BANKS] = { - {0xFF800000, 0xFF880000, 0xFFC00000}, /* 0:000: configuraton 4 */ - {0xFF900000, 0xFF980000, 0xFFC00000}, /* 1:001: configuraton 3 */ - {0x00000000, 0x00000000, 0x00000000}, /* 2:010: configuraton 8 */ - {0x00000000, 0x00000000, 0x00000000}, /* 3:011: configuraton 7 */ - {0xFFE00000, 0xFFF00000, 0xFF800000}, /* 4:100: configuraton 2 */ - {0xFFF00000, 0xFFF80000, 0xFF800000}, /* 5:101: configuraton 1 */ - {0x00000000, 0x00000000, 0x00000000}, /* 6:110: configuraton 6 */ - {0x00000000, 0x00000000, 0x00000000} /* 7:111: configuraton 5 */ -}; - -/* - * include common flash code (for amcc boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(vu_long * addr, flash_info_t * info); -static int write_word(flash_info_t * info, ulong dest, ulong data); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init(void) -{ - unsigned long total_b = 0; - unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS]; - unsigned char *fpga_base = (unsigned char *)CONFIG_SYS_FPGA_BASE; - unsigned char switch_status; - unsigned short index = 0; - int i; - - /* read FPGA base register FPGA_REG0 */ - switch_status = *fpga_base; - - /* check the bitmap of switch status */ - if (switch_status & BOOT_SMALL_FLASH) { - index += BOOT_SMALL_FLASH_VAL; - } - if (switch_status & FLASH_ONBD_N) { - index += FLASH_ONBD_N_VAL; - } - if (switch_status & FLASH_SRAM_SEL) { - index += FLASH_SRAM_SEL_VAL; - } - - DEBUGF("\n"); - DEBUGF("FLASH: Index: %d\n", index); - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - flash_info[i].sector_count = -1; - flash_info[i].size = 0; - - /* check whether the address is 0 */ - if (flash_addr_table[index][i] == 0) { - continue; - } - - /* call flash_get_size() to initialize sector address */ - size_b[i] = - flash_get_size((vu_long *) flash_addr_table[index][i], - &flash_info[i]); - flash_info[i].size = size_b[i]; - if (flash_info[i].flash_id == FLASH_UNKNOWN) { - printf - ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", - i, size_b[i], size_b[i] << 20); - flash_info[i].sector_count = -1; - flash_info[i].size = 0; - } - - /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1, - &flash_info[i]); -#ifdef CONFIG_ENV_IS_IN_FLASH - (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[i]); - (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND, - CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[i]); -#endif - - total_b += flash_info[i].size; - } - - return total_b; -} diff --git a/board/amcc/ocotea/init.S b/board/amcc/ocotea/init.S deleted file mode 100644 index 35085f0a06..0000000000 --- a/board/amcc/ocotea/init.S +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <ppc_asm.tmpl> -#include <config.h> -#include <asm/mmu.h> -#include <asm/ppc4xx.h> - -/************************************************************************** - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - * - *************************************************************************/ - - .section .bootpg,"ax" - .globl tlbtab - -tlbtab: - tlbtab_start - - tlbentry(0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG) - - /* - * TLB entries for SDRAM are not needed on this platform. - * They are dynamically generated in the SPD DDR(2) detection - * routine. - */ - - tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_RWX) - tlbentry(CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_RWX) - tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG) - tlbtab_end diff --git a/board/amcc/ocotea/ocotea.c b/board/amcc/ocotea/ocotea.c deleted file mode 100644 index 5f11f195e8..0000000000 --- a/board/amcc/ocotea/ocotea.c +++ /dev/null @@ -1,387 +0,0 @@ -/* - * Copyright (C) 2004 PaulReynolds@lhsolutions.com - * - * (C) Copyright 2005 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -#include <common.h> -#include "ocotea.h" -#include <asm/processor.h> -#include <spd_sdram.h> -#include <asm/ppc4xx-emac.h> - -DECLARE_GLOBAL_DATA_PTR; - -#define BOOT_SMALL_FLASH 32 /* 00100000 */ -#define FLASH_ONBD_N 2 /* 00000010 */ -#define FLASH_SRAM_SEL 1 /* 00000001 */ - -long int fixed_sdram (void); -void fpga_init (void); - -int board_early_init_f (void) -{ - unsigned long mfr; - unsigned char *fpga_base = (unsigned char *) CONFIG_SYS_FPGA_BASE; - unsigned char switch_status; - unsigned long cs0_base; - unsigned long cs0_size; - unsigned long cs0_twt; - unsigned long cs2_base; - unsigned long cs2_size; - unsigned long cs2_twt; - - /*-------------------------------------------------------------------------+ - | Initialize EBC CONFIG - +-------------------------------------------------------------------------*/ - mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK | - EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK | - EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS | - EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT | - EBC_CFG_PME_DISABLE | EBC_CFG_PR_32); - - /*-------------------------------------------------------------------------+ - | FPGA. Initialize bank 7 with default values. - +-------------------------------------------------------------------------*/ - mtebc(PB7AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)| - EBC_BXAP_BCE_DISABLE| - EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)| - EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)| - EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED| - EBC_BXAP_BEM_WRITEONLY| - EBC_BXAP_PEN_DISABLED); - mtebc(PB7CR, EBC_BXCR_BAS_ENCODE(0x48300000)| - EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT); - - /* read FPGA base register FPGA_REG0 */ - switch_status = *fpga_base; - - if (switch_status & 0x40) { - cs0_base = 0xFFE00000; - cs0_size = EBC_BXCR_BS_2MB; - cs0_twt = 8; - cs2_base = 0xFF800000; - cs2_size = EBC_BXCR_BS_4MB; - cs2_twt = 10; - } else { - cs0_base = 0xFFC00000; - cs0_size = EBC_BXCR_BS_4MB; - cs0_twt = 10; - cs2_base = 0xFF800000; - cs2_size = EBC_BXCR_BS_2MB; - cs2_twt = 8; - } - - /*-------------------------------------------------------------------------+ - | 1 MB FLASH / 1 MB SRAM. Initialize bank 0 with default values. - +-------------------------------------------------------------------------*/ - mtebc(PB0AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs0_twt)| - EBC_BXAP_BCE_DISABLE| - EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)| - EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)| - EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED| - EBC_BXAP_BEM_WRITEONLY| - EBC_BXAP_PEN_DISABLED); - mtebc(PB0CR, EBC_BXCR_BAS_ENCODE(cs0_base)| - cs0_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT); - - /*-------------------------------------------------------------------------+ - | 8KB NVRAM/RTC. Initialize bank 1 with default values. - +-------------------------------------------------------------------------*/ - mtebc(PB1AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(10)| - EBC_BXAP_BCE_DISABLE| - EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)| - EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)| - EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED| - EBC_BXAP_BEM_WRITEONLY| - EBC_BXAP_PEN_DISABLED); - mtebc(PB1CR, EBC_BXCR_BAS_ENCODE(0x48000000)| - EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT); - - /*-------------------------------------------------------------------------+ - | 4 MB FLASH. Initialize bank 2 with default values. - +-------------------------------------------------------------------------*/ - mtebc(PB2AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs2_twt)| - EBC_BXAP_BCE_DISABLE| - EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)| - EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)| - EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED| - EBC_BXAP_BEM_WRITEONLY| - EBC_BXAP_PEN_DISABLED); - mtebc(PB2CR, EBC_BXCR_BAS_ENCODE(cs2_base)| - cs2_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT); - - /*-------------------------------------------------------------------------+ - | FPGA. Initialize bank 7 with default values. - +-------------------------------------------------------------------------*/ - mtebc(PB7AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)| - EBC_BXAP_BCE_DISABLE| - EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)| - EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)| - EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED| - EBC_BXAP_BEM_WRITEONLY| - EBC_BXAP_PEN_DISABLED); - mtebc(PB7CR, EBC_BXCR_BAS_ENCODE(0x48300000)| - EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT); - - /*-------------------------------------------------------------------- - * Setup the interrupt controller polarities, triggers, etc. - *-------------------------------------------------------------------*/ - /* - * Because of the interrupt handling rework to handle 440GX interrupts - * with the common code, we needed to change names of the UIC registers. - * Here the new relationship: - * - * U-Boot name 440GX name - * ----------------------- - * UIC0 UICB0 - * UIC1 UIC0 - * UIC2 UIC1 - * UIC3 UIC2 - */ - mtdcr (UIC1SR, 0xffffffff); /* clear all */ - mtdcr (UIC1ER, 0x00000000); /* disable all */ - mtdcr (UIC1CR, 0x00000009); /* SMI & UIC1 crit are critical */ - mtdcr (UIC1PR, 0xfffffe13); /* per ref-board manual */ - mtdcr (UIC1TR, 0x01c00008); /* per ref-board manual */ - mtdcr (UIC1VR, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (UIC1SR, 0xffffffff); /* clear all */ - - mtdcr (UIC2SR, 0xffffffff); /* clear all */ - mtdcr (UIC2ER, 0x00000000); /* disable all */ - mtdcr (UIC2CR, 0x00000000); /* all non-critical */ - mtdcr (UIC2PR, 0xffffe0ff); /* per ref-board manual */ - mtdcr (UIC2TR, 0x00ffc000); /* per ref-board manual */ - mtdcr (UIC2VR, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (UIC2SR, 0xffffffff); /* clear all */ - - mtdcr (UIC3SR, 0xffffffff); /* clear all */ - mtdcr (UIC3ER, 0x00000000); /* disable all */ - mtdcr (UIC3CR, 0x00000000); /* all non-critical */ - mtdcr (UIC3PR, 0xffffffff); /* per ref-board manual */ - mtdcr (UIC3TR, 0x00ff8c0f); /* per ref-board manual */ - mtdcr (UIC3VR, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (UIC3SR, 0xffffffff); /* clear all */ - - mtdcr (UIC0SR, 0xfc000000); /* clear all */ - mtdcr (UIC0ER, 0x00000000); /* disable all */ - mtdcr (UIC0CR, 0x00000000); /* all non-critical */ - mtdcr (UIC0PR, 0xfc000000); /* */ - mtdcr (UIC0TR, 0x00000000); /* */ - mtdcr (UIC0VR, 0x00000001); /* */ - mfsdr (SDR0_MFR, mfr); - mfr &= ~SDR0_MFR_ECS_MASK; -/* mtsdr(SDR0_MFR, mfr); */ - fpga_init(); - - return 0; -} - - -int checkboard (void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - printf ("Board: Ocotea - AMCC PPC440GX Evaluation Board"); - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc ('\n'); - - return (0); -} - - -phys_size_t initdram (int board_type) -{ - long dram_size = 0; - -#if defined(CONFIG_SPD_EEPROM) - dram_size = spd_sdram (); -#else - dram_size = fixed_sdram (); -#endif - return dram_size; -} - - -#if !defined(CONFIG_SPD_EEPROM) -/************************************************************************* - * fixed sdram init -- doesn't use serial presence detect. - * - * Assumes: 128 MB, non-ECC, non-registered - * PLB @ 133 MHz - * - ************************************************************************/ -long int fixed_sdram (void) -{ - uint reg; - - /*-------------------------------------------------------------------- - * Setup some default - *------------------------------------------------------------------*/ - mtsdram (SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */ - mtsdram (SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ - mtsdram (SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */ - mtsdram (SDRAM0_WDDCTR, 0x00000000); /* wrcp=0 dcd=0 */ - mtsdram (SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */ - - /*-------------------------------------------------------------------- - * Setup for board-specific specific mem - *------------------------------------------------------------------*/ - /* - * Following for CAS Latency = 2.5 @ 133 MHz PLB - */ - mtsdram (SDRAM0_B0CR, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */ - mtsdram (SDRAM0_TR0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */ - /* RA=10 RD=3 */ - mtsdram (SDRAM0_TR1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */ - mtsdram (SDRAM0_RTR, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */ - mtsdram (SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM */ - udelay (400); /* Delay 200 usecs (min) */ - - /*-------------------------------------------------------------------- - * Enable the controller, then wait for DCEN to complete - *------------------------------------------------------------------*/ - mtsdram (SDRAM0_CFG0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */ - for (;;) { - mfsdram (SDRAM0_MCSTS, reg); - if (reg & 0x80000000) - break; - } - - return (128 * 1024 * 1024); /* 128 MB */ -} -#endif /* !defined(CONFIG_SPD_EEPROM) */ - -void fpga_init(void) -{ - unsigned long group; - unsigned long sdr0_pfc0; - unsigned long sdr0_pfc1; - unsigned long sdr0_cust0; - unsigned long pvr; - - mfsdr (SDR0_PFC0, sdr0_pfc0); - mfsdr (SDR0_PFC1, sdr0_pfc1); - group = SDR0_PFC1_EPS_DECODE(sdr0_pfc1); - pvr = get_pvr (); - - sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_GEIE_MASK) | SDR0_PFC0_GEIE_TRE; - if ( ((pvr == PVR_440GX_RA) || (pvr == PVR_440GX_RB)) && ((group == 4) || (group == 5))) { - sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_TRE_MASK) | SDR0_PFC0_TRE_DISABLE; - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_EMS; - out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) | - FPGA_REG2_EXT_INTFACE_ENABLE); - mtsdr (SDR0_PFC0, sdr0_pfc0); - mtsdr (SDR0_PFC1, sdr0_pfc1); - } else { - sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_TRE_MASK) | SDR0_PFC0_TRE_ENABLE; - switch (group) - { - case 0: - case 1: - case 2: - /* CPU trace A */ - out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) | - FPGA_REG2_EXT_INTFACE_ENABLE); - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_EMS; - mtsdr (SDR0_PFC0, sdr0_pfc0); - mtsdr (SDR0_PFC1, sdr0_pfc1); - break; - case 3: - case 4: - case 5: - case 6: - /* CPU trace B - Over EBMI */ - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_CPUTRACE; - mtsdr (SDR0_PFC0, sdr0_pfc0); - mtsdr (SDR0_PFC1, sdr0_pfc1); - out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) | - FPGA_REG2_EXT_INTFACE_DISABLE); - break; - } - } - - /* Initialize the ethernet specific functions in the fpga */ - mfsdr(SDR0_PFC1, sdr0_pfc1); - mfsdr(SDR0_CUST0, sdr0_cust0); - if ( (SDR0_PFC1_EPS_DECODE(sdr0_pfc1) == 4) && - ((SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_GMII) || - (SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_TBI))) - { - if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1) - { - out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK1) | - FPGA_REG3_ENET_GROUP7); - } - else - { - if (SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_GMII) - { - out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) | - FPGA_REG3_ENET_GROUP7); - } - else - { - out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) | - FPGA_REG3_ENET_GROUP8); - } - } - } - else - { - if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1) - { - out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK1) | - FPGA_REG3_ENET_ENCODE1(SDR0_PFC1_EPS_DECODE(sdr0_pfc1))); - } - else - { - out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) | - FPGA_REG3_ENET_ENCODE2(SDR0_PFC1_EPS_DECODE(sdr0_pfc1))); - } - } - out8(FPGA_REG4, FPGA_REG4_GPHY_MODE10 | - FPGA_REG4_GPHY_MODE100 | FPGA_REG4_GPHY_MODE1000 | - FPGA_REG4_GPHY_FRC_DPLX | FPGA_REG4_CONNECT_PHYS); - - /* reset the gigabyte phy if necessary */ - if (SDR0_PFC1_EPS_DECODE(sdr0_pfc1) >= 3) - { - if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1) - { - out8(FPGA_REG3, in8(FPGA_REG3) & ~FPGA_REG3_GIGABIT_RESET_DISABLE); - udelay(10000); - out8(FPGA_REG3, in8(FPGA_REG3) | FPGA_REG3_GIGABIT_RESET_DISABLE); - } - else - { - out8(FPGA_REG2, in8(FPGA_REG2) & ~FPGA_REG2_GIGABIT_RESET_DISABLE); - udelay(10000); - out8(FPGA_REG2, in8(FPGA_REG2) | FPGA_REG2_GIGABIT_RESET_DISABLE); - } - } - - /* - * new Ocotea with Rev. F (pass 3) chips has SMII PHY reset - */ - if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER2) { - out8(FPGA_REG2, in8(FPGA_REG2) & ~FPGA_REG2_SMII_RESET_DISABLE); - udelay(10000); - out8(FPGA_REG2, in8(FPGA_REG2) | FPGA_REG2_SMII_RESET_DISABLE); - } - - /* Turn off the LED's */ - out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_STAT_MASK) | - FPGA_REG3_STAT_LED8_DISAB | FPGA_REG3_STAT_LED4_DISAB | - FPGA_REG3_STAT_LED2_DISAB | FPGA_REG3_STAT_LED1_DISAB); - - return; -} diff --git a/board/amcc/ocotea/ocotea.h b/board/amcc/ocotea/ocotea.h deleted file mode 100644 index 853002f4b9..0000000000 --- a/board/amcc/ocotea/ocotea.h +++ /dev/null @@ -1,125 +0,0 @@ -/* - * (C) Copyright 2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* Board specific FPGA stuff ... */ -#define FPGA_REG0 (CONFIG_SYS_FPGA_BASE + 0x00) -#define FPGA_REG0_SSCG_MASK 0x80 -#define FPGA_REG0_SSCG_DISABLE 0x00 -#define FPGA_REG0_SSCG_ENABLE 0x80 -#define FPGA_REG0_BOOT_MASK 0x40 -#define FPGA_REG0_BOOT_LARGE_FLASH 0x00 -#define FPGA_REG0_BOOT_SMALL_FLASH 0x40 -#define FPGA_REG0_ECLS_MASK 0x38 /* New for Ocotea Rev 2 */ -#define FPGA_REG0_ECLS_0 0x20 /* New for Ocotea Rev 2 */ -#define FPGA_REG0_ECLS_1 0x10 /* New for Ocotea Rev 2 */ -#define FPGA_REG0_ECLS_2 0x08 /* New for Ocotea Rev 2 */ -#define FPGA_REG0_ECLS_VER1 0x00 /* New for Ocotea Rev 2 */ -#define FPGA_REG0_ECLS_VER3 0x08 /* New for Ocotea Rev 2 */ -#define FPGA_REG0_ECLS_VER4 0x10 /* New for Ocotea Rev 2 */ -#define FPGA_REG0_ECLS_VER5 0x18 /* New for Ocotea Rev 2 */ -#define FPGA_REG0_ECLS_VER2 0x20 /* New for Ocotea Rev 2 */ -#define FPGA_REG0_ECLS_VER6 0x28 /* New for Ocotea Rev 2 */ -#define FPGA_REG0_ECLS_VER7 0x30 /* New for Ocotea Rev 2 */ -#define FPGA_REG0_ECLS_VER8 0x38 /* New for Ocotea Rev 2 */ -#define FPGA_REG0_ARBITER_MASK 0x04 -#define FPGA_REG0_ARBITER_EXT 0x00 -#define FPGA_REG0_ARBITER_INT 0x04 -#define FPGA_REG0_ONBOARD_FLASH_MASK 0x02 -#define FPGA_REG0_ONBOARD_FLASH_ENABLE 0x00 -#define FPGA_REG0_ONBOARD_FLASH_DISABLE 0x02 -#define FPGA_REG0_FLASH 0x01 -#define FPGA_REG1 (CONFIG_SYS_FPGA_BASE + 0x01) -#define FPGA_REG1_9772_FSELFBX_MASK 0x80 -#define FPGA_REG1_9772_FSELFBX_6 0x00 -#define FPGA_REG1_9772_FSELFBX_10 0x80 -#define FPGA_REG1_9531_SX_MASK 0x60 -#define FPGA_REG1_9531_SX_33MHZ 0x00 -#define FPGA_REG1_9531_SX_100MHZ 0x20 -#define FPGA_REG1_9531_SX_66MHZ 0x40 -#define FPGA_REG1_9531_SX_133MHZ 0x60 -#define FPGA_REG1_9772_FSELBX_MASK 0x18 -#define FPGA_REG1_9772_FSELBX_4 0x00 -#define FPGA_REG1_9772_FSELBX_6 0x08 -#define FPGA_REG1_9772_FSELBX_8 0x10 -#define FPGA_REG1_9772_FSELBX_10 0x18 -#define FPGA_REG1_SOURCE_MASK 0x07 -#define FPGA_REG1_SOURCE_TC 0x00 -#define FPGA_REG1_SOURCE_66MHZ 0x01 -#define FPGA_REG1_SOURCE_50MHZ 0x02 -#define FPGA_REG1_SOURCE_33MHZ 0x03 -#define FPGA_REG1_SOURCE_25MHZ 0x04 -#define FPGA_REG1_SOURCE_SSDIV1 0x05 -#define FPGA_REG1_SOURCE_SSDIV2 0x06 -#define FPGA_REG1_SOURCE_SSDIV4 0x07 -#define FPGA_REG2 (CONFIG_SYS_FPGA_BASE + 0x02) -#define FPGA_REG2_TC0 0x80 -#define FPGA_REG2_TC1 0x40 -#define FPGA_REG2_TC2 0x20 -#define FPGA_REG2_TC3 0x10 -#define FPGA_REG2_GIGABIT_RESET_DISABLE 0x08 /*Use on Ocotea pass 2 boards*/ -#define FPGA_REG2_EXT_INTFACE_MASK 0x04 -#define FPGA_REG2_EXT_INTFACE_ENABLE 0x00 -#define FPGA_REG2_EXT_INTFACE_DISABLE 0x04 -#define FPGA_REG2_SMII_RESET_DISABLE 0x02 /*Use on Ocotea pass 3 boards*/ -#define FPGA_REG2_DEFAULT_UART1_N 0x01 -#define FPGA_REG3 (CONFIG_SYS_FPGA_BASE + 0x03) -#define FPGA_REG3_GIGABIT_RESET_DISABLE 0x80 /*Use on Ocotea pass 1 boards*/ -#define FPGA_REG3_ENET_MASK1 0x70 /*Use on Ocotea pass 1 boards*/ -#define FPGA_REG3_ENET_MASK2 0xF0 /*Use on Ocotea pass 2 boards*/ -#define FPGA_REG3_ENET_GROUP0 0x00 -#define FPGA_REG3_ENET_GROUP1 0x10 -#define FPGA_REG3_ENET_GROUP2 0x20 -#define FPGA_REG3_ENET_GROUP3 0x30 -#define FPGA_REG3_ENET_GROUP4 0x40 -#define FPGA_REG3_ENET_GROUP5 0x50 -#define FPGA_REG3_ENET_GROUP6 0x60 -#define FPGA_REG3_ENET_GROUP7 0x70 -#define FPGA_REG3_ENET_GROUP8 0x80 /*Use on Ocotea pass 2 boards*/ -#define FPGA_REG3_ENET_ENCODE1(n) ((((unsigned long)(n))&0x07)<<4) /*pass1*/ -#define FPGA_REG3_ENET_DECODE1(n) ((((unsigned long)(n))>>4)&0x07) /*pass1*/ -#define FPGA_REG3_ENET_ENCODE2(n) ((((unsigned long)(n))&0x0F)<<4) /*pass2*/ -#define FPGA_REG3_ENET_DECODE2(n) ((((unsigned long)(n))>>4)&0x0F) /*pass2*/ -#define FPGA_REG3_STAT_MASK 0x0F -#define FPGA_REG3_STAT_LED8_ENAB 0x08 -#define FPGA_REG3_STAT_LED4_ENAB 0x04 -#define FPGA_REG3_STAT_LED2_ENAB 0x02 -#define FPGA_REG3_STAT_LED1_ENAB 0x01 -#define FPGA_REG3_STAT_LED8_DISAB 0x00 -#define FPGA_REG3_STAT_LED4_DISAB 0x00 -#define FPGA_REG3_STAT_LED2_DISAB 0x00 -#define FPGA_REG3_STAT_LED1_DISAB 0x00 -#define FPGA_REG4 (CONFIG_SYS_FPGA_BASE + 0x04) -#define FPGA_REG4_GPHY_MODE10 0x80 -#define FPGA_REG4_GPHY_MODE100 0x40 -#define FPGA_REG4_GPHY_MODE1000 0x20 -#define FPGA_REG4_GPHY_FRC_DPLX 0x10 -#define FPGA_REG4_GPHY_ANEG_DIS 0x08 -#define FPGA_REG4_CONNECT_PHYS 0x04 - - -#define SDR0_CUST0_ENET3_MASK 0x00000080 -#define SDR0_CUST0_ENET3_COPPER 0x00000000 -#define SDR0_CUST0_ENET3_FIBER 0x00000080 -#define SDR0_CUST0_RGMII3_MASK 0x00000070 -#define SDR0_CUST0_RGMII3_ENCODE(n) ((((unsigned long)(n))&0x7)<<4) -#define SDR0_CUST0_RGMII3_DECODE(n) ((((unsigned long)(n))>>4)&0x07) -#define SDR0_CUST0_RGMII3_DISAB 0x00000000 -#define SDR0_CUST0_RGMII3_RTBI 0x00000040 -#define SDR0_CUST0_RGMII3_RGMII 0x00000050 -#define SDR0_CUST0_RGMII3_TBI 0x00000060 -#define SDR0_CUST0_RGMII3_GMII 0x00000070 -#define SDR0_CUST0_ENET2_MASK 0x00000008 -#define SDR0_CUST0_ENET2_COPPER 0x00000000 -#define SDR0_CUST0_ENET2_FIBER 0x00000008 -#define SDR0_CUST0_RGMII2_MASK 0x00000007 -#define SDR0_CUST0_RGMII2_ENCODE(n) ((((unsigned long)(n))&0x7)<<0) -#define SDR0_CUST0_RGMII2_DECODE(n) ((((unsigned long)(n))>>0)&0x07) -#define SDR0_CUST0_RGMII2_DISAB 0x00000000 -#define SDR0_CUST0_RGMII2_RTBI 0x00000004 -#define SDR0_CUST0_RGMII2_RGMII 0x00000005 -#define SDR0_CUST0_RGMII2_TBI 0x00000006 -#define SDR0_CUST0_RGMII2_GMII 0x00000007 diff --git a/board/amcc/taihu/Kconfig b/board/amcc/taihu/Kconfig deleted file mode 100644 index faafb08941..0000000000 --- a/board/amcc/taihu/Kconfig +++ /dev/null @@ -1,16 +0,0 @@ -if TARGET_TAIHU - -config SYS_BOARD - default "taihu" - -config SYS_VENDOR - default "amcc" - -config SYS_CONFIG_NAME - default "taihu" - -config DISPLAY_BOARDINFO - bool - default y - -endif diff --git a/board/amcc/taihu/MAINTAINERS b/board/amcc/taihu/MAINTAINERS deleted file mode 100644 index 2efc254954..0000000000 --- a/board/amcc/taihu/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -TAIHU BOARD -M: John Otken <jotken@softadvances.com> -S: Maintained -F: board/amcc/taihu/ -F: include/configs/taihu.h -F: configs/taihu_defconfig diff --git a/board/amcc/taihu/Makefile b/board/amcc/taihu/Makefile deleted file mode 100644 index 65606fe080..0000000000 --- a/board/amcc/taihu/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = taihu.o flash.o lcd.o update.o diff --git a/board/amcc/taihu/flash.c b/board/amcc/taihu/flash.c deleted file mode 100644 index 0780488888..0000000000 --- a/board/amcc/taihu/flash.c +++ /dev/null @@ -1,1063 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Modified 4/5/2001 - * Wait for completion of each sector erase command issued - * 4/5/2001 - * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com - */ - -#include <common.h> -#include <asm/ppc4xx.h> -#include <asm/processor.h> - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -#undef DEBUG -#ifdef DEBUG -#define DEBUGF(x...) printf(x) -#else -#define DEBUGF(x...) -#endif /* DEBUG */ - -#define CONFIG_SYS_FLASH_CHAR_SIZE unsigned char -#define CONFIG_SYS_FLASH_CHAR_ADDR0 (0x0aaa) -#define CONFIG_SYS_FLASH_CHAR_ADDR1 (0x0555) -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(vu_long * addr, flash_info_t * info); -static void flash_get_offsets(ulong base, flash_info_t * info); -static int write_word(flash_info_t * info, ulong dest, ulong data); -#ifdef FLASH_BASE1_PRELIM -static int write_word_1(flash_info_t * info, ulong dest, ulong data); -static int write_word_2(flash_info_t * info, ulong dest, ulong data); -static int flash_erase_1(flash_info_t * info, int s_first, int s_last); -static int flash_erase_2(flash_info_t * info, int s_first, int s_last); -static ulong flash_get_size_1(vu_long * addr, flash_info_t * info); -static ulong flash_get_size_2(vu_long * addr, flash_info_t * info); -#endif - -unsigned long flash_init(void) -{ - unsigned long size_b0, size_b1=0; - int i; - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here - FIXME XXX */ - - size_b0 = - flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0 << 20); - } - - if (size_b0) { - /* Setup offsets */ - flash_get_offsets(FLASH_BASE0_PRELIM, &flash_info[0]); - /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1, - &flash_info[0]); -#ifdef CONFIG_ENV_IS_IN_FLASH - (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[0]); - (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND, - CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[0]); -#endif - /* Also protect sector containing initial power-up instruction */ - /* (flash_protect() checks address range - other call ignored) */ - (void)flash_protect(FLAG_PROTECT_SET, - 0xFFFFFFFC, 0xFFFFFFFF, &flash_info[0]); - - flash_info[0].size = size_b0; - } -#ifdef FLASH_BASE1_PRELIM - size_b1 = - flash_get_size((vu_long *) FLASH_BASE1_PRELIM, &flash_info[1])*2; - - if (flash_info[1].flash_id == FLASH_UNKNOWN) { - printf("## Unknown FLASH on Bank 1 - Size = 0x%08lx = %ld MB\n", - size_b1, size_b1 << 20); - } - - if (size_b1) { - /* Setup offsets */ - flash_get_offsets(FLASH_BASE1_PRELIM, &flash_info[1]); - flash_info[1].size = size_b1; - } -#endif - return (size_b0 + size_b1); -} - -static void flash_get_offsets(ulong base, flash_info_t * info) -{ - int i; - - /* set up sector start address table */ - if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || - (info->flash_id == FLASH_AM040)) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMLV128U) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000*2); - } - } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_S29GL128N ) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000*2); - } - } else { - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = - base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - } -} - - -void flash_print_info(flash_info_t * info) -{ - int i; - int k; - int size; - int erased; - volatile unsigned long *flash; - - if (info->flash_id == FLASH_UNKNOWN) { - printf("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf("AMD "); - break; - case FLASH_MAN_STM: - printf("STM "); - break; - case FLASH_MAN_FUJ: - printf("FUJITSU "); - break; - case FLASH_MAN_SST: - printf("SST "); - break; - default: - printf("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: - printf("AM29F040 (512 Kbit, uniform sector size)\n"); - break; - case FLASH_AM400B: - printf("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: - printf("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: - printf("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: - printf("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AMD016: - printf("AM29F016D (16 Mbit, uniform sector size)\n"); - break; - case FLASH_AM160B: - printf("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: - printf("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: - printf("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: - printf("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - case FLASH_AM033C: - printf("AM29LV033C (32 Mbit, top boot sector)\n"); - break; - case FLASH_AMLV128U: - printf("AM29LV128U (128 Mbit * 2, top boot sector)\n"); - break; - case FLASH_SST800A: - printf("SST39LF/VF800 (8 Mbit, uniform sector size)\n"); - break; - case FLASH_SST160A: - printf("SST39LF/VF160 (16 Mbit, uniform sector size)\n"); - break; - case FLASH_STMW320DT: - printf ("M29W320DT (32 M, top sector)\n"); - break; - case FLASH_S29GL128N: - printf ("S29GL128N (256 Mbit, uniform sector size)\n"); - break; - default: - printf("Unknown Chip Type\n"); - break; - } - - printf(" Size: %ld KB in %d Sectors\n", - info->size >> 10, info->sector_count); - - printf(" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - /* - * Check if whole sector is erased - */ - if (i != (info->sector_count - 1)) - size = info->start[i + 1] - info->start[i]; - else - size = info->start[0] + info->size - info->start[i]; - erased = 1; - flash = (volatile unsigned long *)info->start[i]; - size = size >> 2; /* divide by 4 for longword access */ - for (k = 0; k < size; k++) { - if (*flash++ != 0xffffffff) { - erased = 0; - break; - } - } - - if ((i % 5) == 0) - printf("\n "); - printf(" %08lX%s%s", - info->start[i], - erased ? " E" : " ", info->protect[i] ? "RO " : " "); - } - printf("\n"); - return; -} - - -/* - * The following code cannot be run from FLASH! - */ -#ifdef FLASH_BASE1_PRELIM -static ulong flash_get_size(vu_long * addr, flash_info_t * info) -{ - if ((ulong)addr == FLASH_BASE1_PRELIM) { - return flash_get_size_2(addr, info); - } else { - return flash_get_size_1(addr, info); - } -} - -static ulong flash_get_size_1(vu_long * addr, flash_info_t * info) -#else -static ulong flash_get_size(vu_long * addr, flash_info_t * info) -#endif -{ - short i; - CONFIG_SYS_FLASH_WORD_SIZE value; - ulong base = (ulong) addr; - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr; - - DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr); - - /* Write auto select command: read Manufacturer ID */ - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00900090; - udelay(1000); - - value = addr2[0]; - DEBUGF("FLASH MANUFACT: %x\n", value); - - switch (value) { - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case (CONFIG_SYS_FLASH_WORD_SIZE) FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - case (CONFIG_SYS_FLASH_WORD_SIZE) SST_MANUFACT: - info->flash_id = FLASH_MAN_SST; - break; - case (CONFIG_SYS_FLASH_WORD_SIZE) STM_MANUFACT: - info->flash_id = FLASH_MAN_STM; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return 0; /* no or unknown flash */ - } - - value = addr2[1]; /* device ID */ - DEBUGF("\nFLASH DEVICEID: %x\n", value); - - switch (value) { - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 512 ko */ - break; - - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_F040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 512 ko */ - break; - - case (CONFIG_SYS_FLASH_WORD_SIZE) STM_ID_M29W040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 512 ko */ - break; - - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_F016D: - info->flash_id += FLASH_AMD016; - info->sector_count = 32; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV033C: - info->flash_id += FLASH_AMDLV033C; - info->sector_count = 64; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - default: - info->flash_id = FLASH_UNKNOWN; - return 0; /* => no or unknown flash */ - } - - /* set up sector start address table */ - if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } - else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMLV128U) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000 * 2); - } else { - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = - base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]); - - /* For AMD29033C flash we need to resend the command of * - * reading flash protection for upper 8 Mb of flash */ - if (i == 32) { - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA; - addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555; - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x90909090; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) - info->protect[i] = 0; - else - info->protect[i] = addr2[2] & 1; - } - - /* issue bank reset to return to read mode */ - addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0; - - return info->size; -} - -static int wait_for_DQ7_1(flash_info_t * info, int sect) -{ - ulong start, now, last; - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = - (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]); - - start = get_timer(0); - last = start; - while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) != - (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf("Timeout\n"); - return -1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc('.'); - last = now; - } - } - return 0; -} - -#ifdef FLASH_BASE1_PRELIM -int flash_erase(flash_info_t * info, int s_first, int s_last) -{ - if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMLV128U) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_S29GL128N) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT)) { - return flash_erase_2(info, s_first, s_last); - } else { - return flash_erase_1(info, s_first, s_last); - } -} - -static int flash_erase_1(flash_info_t * info, int s_first, int s_last) -#else -int flash_erase(flash_info_t * info, int s_first, int s_last) -#endif -{ - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]); - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2; - int flag, prot, sect; - int i; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf("- missing\n"); - } else { - printf("- no sectors to erase\n"); - } - return 1; - } - - if (info->flash_id == FLASH_UNKNOWN) { - printf("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf("\n"); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]); - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00500050; /* block erase */ - for (i = 0; i < 50; i++) - udelay(1000); /* wait 1 ms */ - } else { - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030; /* sector erase */ - } - /* - * Wait for each sector to complete, it's more - * reliable. According to AMD Spec, you must - * issue all erase commands within a specified - * timeout. This has been seen to fail, especially - * if printf()s are included (for debug)!! - */ - wait_for_DQ7_1(info, sect); - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay(1000); - - /* reset to read mode */ - addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0]; - addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ - - printf(" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < 4 && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return rc; - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i = 0; i < 4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return rc; - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return 0; - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -#ifdef FLASH_BASE1_PRELIM -static int write_word(flash_info_t * info, ulong dest, ulong data) -{ - if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMLV128U) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_S29GL128N) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT)) { - return write_word_2(info, dest, data); - } else { - return write_word_1(info, dest, data); - } -} - -static int write_word_1(flash_info_t * info, ulong dest, ulong data) -#else -static int write_word(flash_info_t * info, ulong dest, ulong data) -#endif -{ - ulong *data_ptr = &data; - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]); - volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *)dest; - volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *)data_ptr; - ulong start; - int i; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return 2; - } - - for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) { - int flag; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00A000A0; - - dest2[i] = data2[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer(0); - while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) != - (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080)) { - - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return 1; - } - } - } - - return 0; -} - -#ifdef FLASH_BASE1_PRELIM - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size_2(vu_long * addr, flash_info_t * info) -{ - short i; - CONFIG_SYS_FLASH_CHAR_SIZE value; - ulong base = (ulong) addr; - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr; - - DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr); - - /* Write auto select command: read Manufacturer ID */ - addr2[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA; - addr2[CONFIG_SYS_FLASH_CHAR_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555; - addr2[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x90909090; - udelay(1000); - - value = (CONFIG_SYS_FLASH_CHAR_SIZE)addr2[0]; - DEBUGF("FLASH MANUFACT: %x\n", value); - - switch (value) { - case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case (CONFIG_SYS_FLASH_CHAR_SIZE) FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - case (CONFIG_SYS_FLASH_CHAR_SIZE) SST_MANUFACT: - info->flash_id = FLASH_MAN_SST; - break; - case (CONFIG_SYS_FLASH_CHAR_SIZE) STM_MANUFACT: - info->flash_id = FLASH_MAN_STM; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return 0; /* no or unknown flash */ - } - - value = (CONFIG_SYS_FLASH_CHAR_SIZE)addr2[2]; /* device ID */ - DEBUGF("\nFLASH DEVICEID: %x\n", value); - - switch (value) { - case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_LV040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 512 ko */ - break; - - case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_F040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 512 ko */ - break; - - case (CONFIG_SYS_FLASH_CHAR_SIZE) STM_ID_M29W040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 512 ko */ - break; - - case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_F016D: - info->flash_id += FLASH_AMD016; - info->sector_count = 32; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_LV033C: - info->flash_id += FLASH_AMDLV033C; - info->sector_count = 64; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_MIRROR: - if ((CONFIG_SYS_FLASH_CHAR_SIZE)addr2[0x1c] == (CONFIG_SYS_FLASH_CHAR_SIZE)AMD_ID_LV128U_2 - && (CONFIG_SYS_FLASH_CHAR_SIZE)addr2[0x1e] == (CONFIG_SYS_FLASH_CHAR_SIZE)AMD_ID_LV128U_3) { - info->flash_id += FLASH_AMLV128U; - info->sector_count = 256; - info->size = 0x01000000; - } else if ((CONFIG_SYS_FLASH_CHAR_SIZE)addr2[0x1c] == (CONFIG_SYS_FLASH_CHAR_SIZE)AMD_ID_GL128N_2 - && (CONFIG_SYS_FLASH_CHAR_SIZE)addr2[0x1e] == (CONFIG_SYS_FLASH_CHAR_SIZE)AMD_ID_GL128N_3 ) { - info->flash_id += FLASH_S29GL128N; - info->sector_count = 128; - info->size = 0x01000000; - } - else - info->flash_id = FLASH_UNKNOWN; - break; /* => 2 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - return 0; /* => no or unknown flash */ - } - - /* set up sector start address table */ - if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMLV128U) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_S29GL128N ) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00020000); - } else { - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = - base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]); - - /* For AMD29033C flash we need to resend the command of * - * reading flash protection for upper 8 Mb of flash */ - if (i == 32) { - addr2[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA; - addr2[CONFIG_SYS_FLASH_CHAR_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555; - addr2[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x90909090; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) - info->protect[i] = 0; - else - info->protect[i] = (CONFIG_SYS_FLASH_CHAR_SIZE)addr2[4] & 1; - } - - /* issue bank reset to return to read mode */ - addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xF0F0F0F0; - return info->size; -} - -static int wait_for_DQ7_2(flash_info_t * info, int sect) -{ - ulong start, now, last; - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = - (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]); - - start = get_timer(0); - last = start; - while (((CONFIG_SYS_FLASH_WORD_SIZE)addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x80808080) != - (CONFIG_SYS_FLASH_WORD_SIZE) 0x80808080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf("Timeout\n"); - return -1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc('.'); - last = now; - } - } - return 0; -} - -static int flash_erase_2(flash_info_t * info, int s_first, int s_last) -{ - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]); - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2; - int flag, prot, sect; - int i; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf("- missing\n"); - } else { - printf("- no sectors to erase\n"); - } - return 1; - } - - if (info->flash_id == FLASH_UNKNOWN) { - printf("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf("\n"); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]); - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { - addr[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA; - addr[CONFIG_SYS_FLASH_CHAR_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555; - addr[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x80808080; - addr[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA; - addr[CONFIG_SYS_FLASH_CHAR_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555; - addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x50505050; /* block erase */ - for (i = 0; i < 50; i++) - udelay(1000); /* wait 1 ms */ - } else { - addr[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA; - addr[CONFIG_SYS_FLASH_CHAR_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555; - addr[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x80808080; - addr[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA; - addr[CONFIG_SYS_FLASH_CHAR_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555; - addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x30303030; /* sector erase */ - } - /* - * Wait for each sector to complete, it's more - * reliable. According to AMD Spec, you must - * issue all erase commands within a specified - * timeout. This has been seen to fail, especially - * if printf()s are included (for debug)!! - */ - wait_for_DQ7_2(info, sect); - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay(1000); - - /* reset to read mode */ - addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0]; - addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xF0F0F0F0; /* reset bank */ - - printf(" done\n"); - return 0; -} - -static int write_word_2(flash_info_t * info, ulong dest, ulong data) -{ - ulong *data_ptr = &data; - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]); - volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *)dest; - volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *)data_ptr; - ulong start; - int i; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return 2; - } - - for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) { - int flag; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr2[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA; - addr2[CONFIG_SYS_FLASH_CHAR_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555; - addr2[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xA0A0A0A0; - - dest2[i] = data2[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer(0); - while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x80808080) != - (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x80808080)) { - - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return 1; - } - } - } - - return 0; -} - -#endif /* FLASH_BASE1_PRELIM */ diff --git a/board/amcc/taihu/lcd.c b/board/amcc/taihu/lcd.c deleted file mode 100644 index c7c7fa4439..0000000000 --- a/board/amcc/taihu/lcd.c +++ /dev/null @@ -1,237 +0,0 @@ -/* - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <config.h> -#include <common.h> -#include <command.h> -#include <asm/io.h> -#include <asm/ppc4xx-gpio.h> - -#define LCD_CMD_ADDR 0x50100002 -#define LCD_DATA_ADDR 0x50100003 -#define LCD_BLK_CTRL CPLD_REG1_ADDR - -static char *amcc_logo = "AMCC 405EP TAIHU EVALUATION KIT"; -static int addr_flag = 0x80; - -static void lcd_bl_ctrl(char val) -{ - out_8((u8 *) LCD_BLK_CTRL, in_8((u8 *) LCD_BLK_CTRL) | val); -} - -static void lcd_putc(int val) -{ - int i = 100; - char addr; - - while (i--) { - if ((in_8((u8 *) LCD_CMD_ADDR) & 0x80) != 0x80) { /*BF = 1 ?*/ - udelay(50); - break; - } - udelay(50); - } - - if (in_8((u8 *) LCD_CMD_ADDR) & 0x80) { - printf("LCD is busy\n"); - return; - } - - addr = in_8((u8 *) LCD_CMD_ADDR); - udelay(50); - if ((addr != 0) && (addr % 0x10 == 0)) { - addr_flag ^= 0x40; - out_8((u8 *) LCD_CMD_ADDR, addr_flag); - } - - udelay(50); - out_8((u8 *) LCD_DATA_ADDR, val); - udelay(50); -} - -static void lcd_puts(char *s) -{ - char *p = s; - int i = 100; - - while (i--) { - if ((in_8((u8 *) LCD_CMD_ADDR) & 0x80) != 0x80) { /*BF = 1 ?*/ - udelay(50); - break; - } - udelay(50); - } - - if (in_8((u8 *) LCD_CMD_ADDR) & 0x80) { - printf("LCD is busy\n"); - return; - } - - while (*p) - lcd_putc(*p++); -} - -static void lcd_put_logo(void) -{ - int i = 100; - char *p = amcc_logo; - - while (i--) { - if ((in_8((u8 *) LCD_CMD_ADDR) & 0x80) != 0x80) { /*BF = 1 ?*/ - udelay(50); - break; - } - udelay(50); - } - - if (in_8((u8 *) LCD_CMD_ADDR) & 0x80) { - printf("LCD is busy\n"); - return; - } - - out_8((u8 *) LCD_CMD_ADDR, 0x80); - while (*p) - lcd_putc(*p++); -} - -int lcd_init(void) -{ - puts("LCD: "); - out_8((u8 *) LCD_CMD_ADDR, 0x38); /* set function:8-bit,2-line,5x7 font type */ - udelay(50); - out_8((u8 *) LCD_CMD_ADDR, 0x0f); /* set display on,cursor on,blink on */ - udelay(50); - out_8((u8 *) LCD_CMD_ADDR, 0x01); /* display clear */ - udelay(2000); - out_8((u8 *) LCD_CMD_ADDR, 0x06); /* set entry */ - udelay(50); - lcd_bl_ctrl(0x02); /* set backlight on */ - lcd_put_logo(); - puts("ready\n"); - - return 0; -} - -static int do_lcd_clear (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - out_8((u8 *) LCD_CMD_ADDR, 0x01); - udelay(2000); - - return 0; -} - -static int do_lcd_puts (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - if (argc < 2) - return cmd_usage(cmdtp); - - lcd_puts(argv[1]); - - return 0; -} - -static int do_lcd_putc (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - if (argc < 2) - return cmd_usage(cmdtp); - - lcd_putc((char)argv[1][0]); - - return 0; -} - -static int do_lcd_cur (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - ulong count; - ulong dir; - char cur_addr; - - if (argc < 3) - return cmd_usage(cmdtp); - - count = simple_strtoul(argv[1], NULL, 16); - if (count > 31) { - printf("unable to shift > 0x20\n"); - count = 0; - } - - dir = simple_strtoul(argv[2], NULL, 16); - cur_addr = in_8((u8 *) LCD_CMD_ADDR); - udelay(50); - - if (dir == 0x0) { - if (addr_flag == 0x80) { - if (count >= (cur_addr & 0xf)) { - out_8((u8 *) LCD_CMD_ADDR, 0x80); - udelay(50); - count = 0; - } - } else { - if (count >= ((cur_addr & 0x0f) + 0x0f)) { - out_8((u8 *) LCD_CMD_ADDR, 0x80); - addr_flag = 0x80; - udelay(50); - count = 0x0; - } else if (count >= ( cur_addr & 0xf)) { - count -= cur_addr & 0xf ; - out_8((u8 *) LCD_CMD_ADDR, 0x80 | 0xf); - addr_flag = 0x80; - udelay(50); - } - } - } else { - if (addr_flag == 0x80) { - if (count >= (0x1f - (cur_addr & 0xf))) { - count = 0x0; - addr_flag = 0xc0; - out_8((u8 *) LCD_CMD_ADDR, 0xc0 | 0xf); - udelay(50); - } else if ((count + (cur_addr & 0xf ))>= 0x0f) { - count = count + (cur_addr & 0xf) - 0x0f; - addr_flag = 0xc0; - out_8((u8 *) LCD_CMD_ADDR, 0xc0); - udelay(50); - } - } else if ((count + (cur_addr & 0xf )) >= 0x0f) { - count = 0x0; - out_8((u8 *) LCD_CMD_ADDR, 0xC0 | 0x0F); - udelay(50); - } - } - while (count--) { - if (dir == 0) - out_8((u8 *) LCD_CMD_ADDR, 0x10); - else - out_8((u8 *) LCD_CMD_ADDR, 0x14); - udelay(50); - } - - return 0; -} - -U_BOOT_CMD( - lcd_cls, 1, 1, do_lcd_clear, - "lcd clear display", - "" -); - -U_BOOT_CMD( - lcd_puts, 2, 1, do_lcd_puts, - "display string on lcd", - "<string> - <string> to be displayed" -); - -U_BOOT_CMD( - lcd_putc, 2, 1, do_lcd_putc, - "display char on lcd", - "<char> - <char> to be displayed" -); - -U_BOOT_CMD( - lcd_cur, 3, 1, do_lcd_cur, - "shift cursor on lcd", - "<count> <dir> - shift cursor on lcd <count> times, direction is <dir> \n" - " <count> - 0..31\n" - " <dir> - 0=backward 1=forward" -); diff --git a/board/amcc/taihu/taihu.c b/board/amcc/taihu/taihu.c deleted file mode 100644 index fcb893633a..0000000000 --- a/board/amcc/taihu/taihu.c +++ /dev/null @@ -1,180 +0,0 @@ -/* - * (C) Copyright 2000-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2005-2007 - * Beijing UD Technology Co., Ltd., taihusupport@amcc.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <common.h> -#include <command.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <spi.h> -#include <netdev.h> -#include <asm/ppc4xx-gpio.h> - -extern int lcd_init(void); - -/* - * board_early_init_f - */ -int board_early_init_f(void) -{ - lcd_init(); - - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr(UIC0ER, 0x00000000); /* disable all ints */ - mtdcr(UIC0CR, 0x00000000); - mtdcr(UIC0PR, 0xFFFF7F00); /* set int polarities */ - mtdcr(UIC0TR, 0x00000000); /* set int trigger levels */ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ - - mtebc(PB3AP, CONFIG_SYS_EBC_PB3AP); /* memory bank 3 (CPLD_LCM) initialization */ - mtebc(PB3CR, CONFIG_SYS_EBC_PB3CR); - - /* - * Configure CPC0_PCI to enable PerWE as output - * and enable the internal PCI arbiter - */ - mtdcr(CPC0_PCI, CPC0_PCI_SPE | CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN); - - return 0; -} - -/* - * Check Board Identity: - */ -int checkboard(void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - puts("Board: Taihu - AMCC PPC405EP Evaluation Board"); - - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc('\n'); - - return 0; -} - -static int do_sw_stat(cmd_tbl_t* cmd_tp, int flags, int argc, char * const argv[]) -{ - char stat; - int i; - - stat = in_8((u8 *) CPLD_REG0_ADDR); - printf("SW2 status: "); - for (i=0; i<4; i++) /* 4-position */ - printf("%d:%s ", i, stat & (0x08 >> i)?"on":"off"); - printf("\n"); - return 0; -} - -U_BOOT_CMD ( - sw2_stat, 1, 1, do_sw_stat, - "show status of switch 2", - "" -); - -static int do_led_ctl(cmd_tbl_t* cmd_tp, int flags, int argc, char * const argv[]) -{ - int led_no; - - if (argc != 3) - return cmd_usage(cmd_tp); - - led_no = simple_strtoul(argv[1], NULL, 16); - if (led_no != 1 && led_no != 2) - return cmd_usage(cmd_tp); - - if (strcmp(argv[2],"off") == 0x0) { - if (led_no == 1) - gpio_write_bit(30, 1); - else - gpio_write_bit(31, 1); - } else if (strcmp(argv[2],"on") == 0x0) { - if (led_no == 1) - gpio_write_bit(30, 0); - else - gpio_write_bit(31, 0); - } else { - return cmd_usage(cmd_tp); - } - - return 0; -} - -U_BOOT_CMD ( - led_ctl, 3, 1, do_led_ctl, - "make led 1 or 2 on or off", - "<led_no> <on/off> - make led <led_no> on/off,\n" - "\tled_no is 1 or 2" -); - -#define SPI_CS_GPIO0 0 -#define SPI_SCLK_GPIO14 14 -#define SPI_DIN_GPIO15 15 -#define SPI_DOUT_GPIO16 16 - -void spi_scl(int bit) -{ - gpio_write_bit(SPI_SCLK_GPIO14, bit); -} - -void spi_sda(int bit) -{ - gpio_write_bit(SPI_DOUT_GPIO16, bit); -} - -unsigned char spi_read(void) -{ - return (unsigned char)gpio_read_in_bit(SPI_DIN_GPIO15); -} - -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - return bus == 0 && cs == 0; -} - -void spi_cs_activate(struct spi_slave *slave) -{ - gpio_write_bit(SPI_CS_GPIO0, 1); -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - gpio_write_bit(SPI_CS_GPIO0, 0); -} - -#ifdef CONFIG_PCI -static unsigned char int_lines[32] = { - 29, 30, 27, 28, 29, 30, 25, 27, - 29, 30, 27, 28, 29, 30, 27, 28, - 29, 30, 27, 28, 29, 30, 27, 28, - 29, 30, 27, 28, 29, 30, 27, 28}; - -static void taihu_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev) -{ - unsigned char int_line = int_lines[PCI_DEV(dev) & 31]; - - pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line); -} - -int pci_pre_init(struct pci_controller *hose) -{ - hose->fixup_irq = taihu_pci_fixup_irq; - return 1; -} -#endif /* CONFIG_PCI */ - -int board_eth_init(bd_t *bis) -{ - cpu_eth_init(bis); - return pci_eth_init(bis); -} diff --git a/board/amcc/taihu/update.c b/board/amcc/taihu/update.c deleted file mode 100644 index ace217d70a..0000000000 --- a/board/amcc/taihu/update.c +++ /dev/null @@ -1,116 +0,0 @@ -/* - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <config.h> -#include <common.h> -#include <command.h> -#include <asm/processor.h> -#include <i2c.h> - -#define PCI_M66EN 0x10 - -static uchar buf_33[] = -{ - 0xb5, /* 0x00:hce =1, bss = 0, pae=1, ppdv= 0b10,spe = 1,ebw=0b01*/ - 0x80, /* 0x01~0x03:ptm1ms =0x80000001 */ - 0x00, - 0x00, - 0x00, /* 0x04~0x06:ptm1la = 0x00000000 */ - 0x00, - 0x00, - 0x00, /* 0x07~0x09:ptm2ma = 0x00000000 */ - 0x00, - 0x00, - 0x00, /* 0x0a~0x0c:ptm2la = 0x00000000 */ - 0x00, - 0x00, - 0x10, /* 0x0d~0x0e:vendor id 0x1014*/ - 0x14, - 0x00, /* 0x0f~0x10:device id 0x0000*/ - 0x00, - 0x00, /* 0x11:revision 0x00 */ - 0x00, /* 0x12~0x14:class 0x000000 */ - 0x00, - 0x00, - 0x10, /* 0x15~0x16:subsystem vendor id */ - 0xe8, - 0x00, /* 0x17~0x18:subsystem device id */ - 0x00, - 0x61, /* 0x19: opdv=0b01,cbdv=0b10,ccdv=0b00,ptm2ms_ena=0, ptm1ms_ena=1 */ - 0x68, /* 0x1a: rpci=1,fbmul=0b1010,epdv=0b00 */ - 0x2d, /* 0x1b: fwdvb=0b101,fwdva=0b101 */ - 0x82, /* 0x1c: pllr=1,sscs=0,mpdv=0b00,tun[22-23]=0b10 */ - 0xbe, /* 0x1d: tun[24-31]=0xbe */ - 0x00, - 0x00 -}; - -static uchar buf_66[] = -{ - 0xb5, /* 0x00:hce =1, bss = 0, pae=1, ppdv= 0b10,spe = 1,ebw=0b01*/ - 0x80, /* 0x01~0x03:ptm1ms =0x80000001 */ - 0x00, - 0x00, - 0x00, /* 0x04~0x06:ptm1la = 0x00000000 */ - 0x00, - 0x00, - 0x00, /* 0x07~0x09:ptm2ma = 0x00000000 */ - 0x00, - 0x00, - 0x00, /* 0x0a~0x0c:ptm2la = 0x00000000 */ - 0x00, - 0x00, - 0x10, /* 0x0d~0x0e:vendor id 0x1014*/ - 0x14, - 0x00, /* 0x0f~0x10:device id 0x0000*/ - 0x00, - 0x00, /* 0x11:revision 0x00 */ - 0x00, /* 0x12~0x14:class 0x000000 */ - 0x00, - 0x00, - 0x10, /* 0x15~0x16:subsystem vendor id */ - 0xe8, - 0x00, /* 0x17~0x18:subsystem device id */ - 0x00, - 0x61, /* 0x19: opdv=0b01,cbdv=0b10,ccdv=0b00,ptm2ms_ena=0, ptm1ms_ena=1 */ - 0x68, /* 0x1a: rpci=1,fbmul=0b1010,epdv=0b00 */ - 0x2d, /* 0x1b: fwdvb=0b101,fwdva=0b101 */ - 0x82, /* 0x1c: pllr=1,sscs=0,mpdv=0b00,tun[22-23]=0b10 */ - 0xbe, /* 0x1d: tun[24-31]=0xbe */ - 0x00, - 0x00 -}; - -static int update_boot_eeprom(cmd_tbl_t* cmdtp, int flag, int argc, char * const argv[]) -{ - ulong len = 0x20; - uchar chip = CONFIG_SYS_I2C_EEPROM_ADDR; - uchar *pbuf; - uchar base; - int i; - - if ((*(volatile char*)CPLD_REG0_ADDR & PCI_M66EN) != PCI_M66EN) { - pbuf = buf_33; - base = 0x00; - } else { - pbuf = buf_66; - base = 0x40; - } - - for (i = 0; i< len; i++, base++) { - if (i2c_write(chip, base, 1, &pbuf[i],1)!= 0) { - printf("i2c_write fail\n"); - return 1; - } - udelay(11000); - } - - return 0; -} - -U_BOOT_CMD ( - update_boot_eeprom, 1, 1, update_boot_eeprom, - "update boot eeprom content", - "" -); diff --git a/board/amcc/taishan/Kconfig b/board/amcc/taishan/Kconfig deleted file mode 100644 index 9ad8a4ce64..0000000000 --- a/board/amcc/taishan/Kconfig +++ /dev/null @@ -1,16 +0,0 @@ -if TARGET_TAISHAN - -config SYS_BOARD - default "taishan" - -config SYS_VENDOR - default "amcc" - -config SYS_CONFIG_NAME - default "taishan" - -config DISPLAY_BOARDINFO - bool - default y - -endif diff --git a/board/amcc/taishan/MAINTAINERS b/board/amcc/taishan/MAINTAINERS deleted file mode 100644 index d9d80bf1c2..0000000000 --- a/board/amcc/taishan/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -TAISHAN BOARD -M: Stefan Roese <sr@denx.de> -S: Maintained -F: board/amcc/taishan/ -F: include/configs/taishan.h -F: configs/taishan_defconfig diff --git a/board/amcc/taishan/Makefile b/board/amcc/taishan/Makefile deleted file mode 100644 index 04e93cc0da..0000000000 --- a/board/amcc/taishan/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2007 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = taishan.o lcd.o update.o showinfo.o -extra-y += init.o diff --git a/board/amcc/taishan/config.mk b/board/amcc/taishan/config.mk deleted file mode 100644 index 6de8b591b9..0000000000 --- a/board/amcc/taishan/config.mk +++ /dev/null @@ -1,20 +0,0 @@ -# -# (C) Copyright 2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# -# AMCC 440GX Reference Platform (Taishan) board -# - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 -endif diff --git a/board/amcc/taishan/init.S b/board/amcc/taishan/init.S deleted file mode 100644 index ab1bb34fb8..0000000000 --- a/board/amcc/taishan/init.S +++ /dev/null @@ -1,35 +0,0 @@ -/* - * (C) Copyright 2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <ppc_asm.tmpl> -#include <asm/mmu.h> -#include <config.h> -#include <asm/ppc4xx.h> - -/************************************************************************** - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - * - *************************************************************************/ - - .section .bootpg,"ax" - .globl tlbtab - -tlbtab: - tlbtab_start - tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG) - tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG) - tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_RWX ) - tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG ) - tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG ) - tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG ) - tlbtab_end diff --git a/board/amcc/taishan/lcd.c b/board/amcc/taishan/lcd.c deleted file mode 100644 index 124b81ee0b..0000000000 --- a/board/amcc/taishan/lcd.c +++ /dev/null @@ -1,358 +0,0 @@ -/* - * (C) Copyright 2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <config.h> -#include <common.h> -#include <command.h> -#include <i2c.h> -#include <miiphy.h> - -#ifdef CONFIG_TAISHAN - -#define LCD_DELAY_NORMAL_US 100 -#define LCD_DELAY_NORMAL_MS 2 -#define LCD_CMD_ADDR ((volatile char *)(CONFIG_SYS_EBC2_LCM_BASE)) -#define LCD_DATA_ADDR ((volatile char *)(CONFIG_SYS_EBC2_LCM_BASE+1)) -#define LCD_BLK_CTRL ((volatile char *)(CONFIG_SYS_EBC1_FPGA_BASE+0x2)) - -static int g_lcd_init_b = 0; -static char *amcc_logo = " AMCC TAISHAN 440GX EvalBoard"; -static char addr_flag = 0x80; - -static void lcd_bl_ctrl(char val) -{ - char cpld_val; - - cpld_val = *LCD_BLK_CTRL; - *LCD_BLK_CTRL = val | cpld_val; -} - -static void lcd_putc(char val) -{ - int i = 100; - char addr; - - while (i--) { - if ((*LCD_CMD_ADDR & 0x80) != 0x80) { /*BF = 1 ? */ - udelay(LCD_DELAY_NORMAL_US); - break; - } - udelay(LCD_DELAY_NORMAL_US); - } - - if (*LCD_CMD_ADDR & 0x80) { - printf("LCD is busy\n"); - return; - } - - addr = *LCD_CMD_ADDR; - udelay(LCD_DELAY_NORMAL_US); - if ((addr != 0) && (addr % 0x10 == 0)) { - addr_flag ^= 0x40; - *LCD_CMD_ADDR = addr_flag; - } - - udelay(LCD_DELAY_NORMAL_US); - *LCD_DATA_ADDR = val; - udelay(LCD_DELAY_NORMAL_US); -} - -static void lcd_puts(char *s) -{ - char *p = s; - int i = 100; - - while (i--) { - if ((*LCD_CMD_ADDR & 0x80) != 0x80) { /*BF = 1 ? */ - udelay(LCD_DELAY_NORMAL_US); - break; - } - udelay(LCD_DELAY_NORMAL_US); - } - - if (*LCD_CMD_ADDR & 0x80) { - printf("LCD is busy\n"); - return; - } - - while (*p) - lcd_putc(*p++); -} - -static void lcd_put_logo(void) -{ - int i = 100; - char *p = amcc_logo; - - while (i--) { - if ((*LCD_CMD_ADDR & 0x80) != 0x80) { /*BF = 1 ? */ - udelay(LCD_DELAY_NORMAL_US); - break; - } - udelay(LCD_DELAY_NORMAL_US); - } - - if (*LCD_CMD_ADDR & 0x80) { - printf("LCD is busy\n"); - return; - } - - *LCD_CMD_ADDR = 0x80; - while (*p) - lcd_putc(*p++); -} - -int lcd_init(void) -{ - if (g_lcd_init_b == 0) { - puts("LCD: "); - mdelay(100); /* Waiting for the LCD initialize */ - - *LCD_CMD_ADDR = 0x38; /*set function:8-bit,2-line,5x7 font type */ - udelay(LCD_DELAY_NORMAL_US); - - *LCD_CMD_ADDR = 0x0f; /*set display on,cursor on,blink on */ - udelay(LCD_DELAY_NORMAL_US); - - *LCD_CMD_ADDR = 0x01; /*display clear */ - mdelay(LCD_DELAY_NORMAL_MS); - - *LCD_CMD_ADDR = 0x06; /*set entry */ - udelay(LCD_DELAY_NORMAL_US); - - lcd_bl_ctrl(0x02); - lcd_put_logo(); - - puts(" ready\n"); - g_lcd_init_b = 1; - } - - return 0; -} - -static int do_lcd_test(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - lcd_init(); - return 0; -} - -static int do_lcd_clear(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - *LCD_CMD_ADDR = 0x01; - mdelay(LCD_DELAY_NORMAL_MS); - return 0; -} -static int do_lcd_puts(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - if (argc < 2) - return cmd_usage(cmdtp); - - lcd_puts(argv[1]); - return 0; -} -static int do_lcd_putc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - if (argc < 2) - return cmd_usage(cmdtp); - - lcd_putc((char)argv[1][0]); - return 0; -} -static int do_lcd_cur(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - ulong count; - ulong dir; - char cur_addr; - - if (argc < 3) - return cmd_usage(cmdtp); - - count = simple_strtoul(argv[1], NULL, 16); - if (count > 31) { - printf("unable to shift > 0x20\n"); - count = 0; - } - - dir = simple_strtoul(argv[2], NULL, 16); - cur_addr = *LCD_CMD_ADDR; - udelay(LCD_DELAY_NORMAL_US); - if (dir == 0x0) { - if (addr_flag == 0x80) { - if (count >= (cur_addr & 0xf)) { - *LCD_CMD_ADDR = 0x80; - udelay(LCD_DELAY_NORMAL_US); - count = 0; - } - } else { - if (count >= ((cur_addr & 0x0f) + 0x0f)) { - *LCD_CMD_ADDR = 0x80; - addr_flag = 0x80; - udelay(LCD_DELAY_NORMAL_US); - count = 0x0; - } else if (count >= (cur_addr & 0xf)) { - count -= cur_addr & 0xf; - *LCD_CMD_ADDR = 0x80 | 0xf; - addr_flag = 0x80; - udelay(LCD_DELAY_NORMAL_US); - } - } - } else { - if (addr_flag == 0x80) { - if (count >= (0x1f - (cur_addr & 0xf))) { - count = 0x0; - addr_flag = 0xc0; - *LCD_CMD_ADDR = 0xc0 | 0xf; - udelay(LCD_DELAY_NORMAL_US); - } else if ((count + (cur_addr & 0xf)) >= 0x0f) { - count = count + (cur_addr & 0xf) - 0x0f; - addr_flag = 0xc0; - *LCD_CMD_ADDR = 0xc0; - udelay(LCD_DELAY_NORMAL_US); - } - } else if ((count + (cur_addr & 0xf)) >= 0x0f) { - count = 0x0; - *LCD_CMD_ADDR = 0xc0 | 0xf; - udelay(LCD_DELAY_NORMAL_US); - } - } - - while (count--) { - if (dir == 0) { - *LCD_CMD_ADDR = 0x10; - } else { - *LCD_CMD_ADDR = 0x14; - } - udelay(LCD_DELAY_NORMAL_US); - } - - return 0; -} - -U_BOOT_CMD(lcd_test, 1, 1, do_lcd_test, "lcd test display", ""); -U_BOOT_CMD(lcd_cls, 1, 1, do_lcd_clear, "lcd clear display", ""); -U_BOOT_CMD(lcd_puts, 2, 1, do_lcd_puts, - "display string on lcd", - "<string> - <string> to be displayed"); -U_BOOT_CMD(lcd_putc, 2, 1, do_lcd_putc, - "display char on lcd", - "<char> - <char> to be displayed"); -U_BOOT_CMD(lcd_cur, 3, 1, do_lcd_cur, - "shift cursor on lcd", - "<count> <dir>- shift cursor on lcd <count> times, direction is <dir> \n" - " <count> - 0~31\n" " <dir> - 0,backward; 1, forward"); - -#if 0 /* test-only */ -void set_phy_loopback_mode(void) -{ - char devemac2[32]; - char devemac3[32]; - - sprintf(devemac2, "%s2", CONFIG_EMAC_DEV_NAME); - sprintf(devemac3, "%s3", CONFIG_EMAC_DEV_NAME); - -#if 0 - unsigned short reg_short; - - miiphy_read(devemac2, 0x1, 1, ®_short); - if (reg_short & 0x04) { - /* - * printf("EMAC2 link up,do nothing\n"); - */ - } else { - udelay(1000); - miiphy_write(devemac2, 0x1, 0, 0x6000); - udelay(1000); - miiphy_read(devemac2, 0x1, 0, ®_short); - if (reg_short != 0x6000) { - printf - ("\nEMAC2 error set LOOPBACK mode error,reg2[0]=%x\n", - reg_short); - } - } - - miiphy_read(devemac3, 0x3, 1, ®_short); - if (reg_short & 0x04) { - /* - * printf("EMAC3 link up,do nothing\n"); - */ - } else { - udelay(1000); - miiphy_write(devemac3, 0x3, 0, 0x6000); - udelay(1000); - miiphy_read(devemac3, 0x3, 0, ®_short); - if (reg_short != 0x6000) { - printf - ("\nEMAC3 error set LOOPBACK mode error,reg2[0]=%x\n", - reg_short); - } - } -#else - /* Set PHY as LOOPBACK MODE, for Linux emac initializing */ - miiphy_write(devemac2, CONFIG_PHY2_ADDR, 0, 0x6000); - udelay(1000); - miiphy_write(devemac3, CONFIG_PHY3_ADDR, 0, 0x6000); - udelay(1000); -#endif /* 0 */ -} - -void set_phy_normal_mode(void) -{ - char devemac2[32]; - char devemac3[32]; - unsigned short reg_short; - - sprintf(devemac2, "%s2", CONFIG_EMAC_DEV_NAME); - sprintf(devemac3, "%s3", CONFIG_EMAC_DEV_NAME); - - /* Set phy of EMAC2 */ - miiphy_read(devemac2, CONFIG_PHY2_ADDR, 0x16, ®_short); - reg_short &= ~(0x7); - reg_short |= 0x6; /* RGMII DLL Delay */ - miiphy_write(devemac2, CONFIG_PHY2_ADDR, 0x16, reg_short); - - miiphy_read(devemac2, CONFIG_PHY2_ADDR, 0x17, ®_short); - reg_short &= ~(0x40); - miiphy_write(devemac2, CONFIG_PHY2_ADDR, 0x17, reg_short); - - miiphy_write(devemac2, CONFIG_PHY2_ADDR, 0x1c, 0x74f0); - - /* Set phy of EMAC3 */ - miiphy_read(devemac3, CONFIG_PHY3_ADDR, 0x16, ®_short); - reg_short &= ~(0x7); - reg_short |= 0x6; /* RGMII DLL Delay */ - miiphy_write(devemac3, CONFIG_PHY3_ADDR, 0x16, reg_short); - - miiphy_read(devemac3, CONFIG_PHY3_ADDR, 0x17, ®_short); - reg_short &= ~(0x40); - miiphy_write(devemac3, CONFIG_PHY3_ADDR, 0x17, reg_short); - - miiphy_write(devemac3, CONFIG_PHY3_ADDR, 0x1c, 0x74f0); -} -#endif /* 0 - test only */ - -static int do_led_test_off(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - volatile unsigned int *GpioOr = - (volatile unsigned int *)(CONFIG_SYS_PERIPHERAL_BASE + 0x700); - *GpioOr |= 0x00300000; - return 0; -} - -static int do_led_test_on(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - volatile unsigned int *GpioOr = - (volatile unsigned int *)(CONFIG_SYS_PERIPHERAL_BASE + 0x700); - *GpioOr &= ~0x00300000; - return 0; -} - -U_BOOT_CMD(ledon, 1, 1, do_led_test_on, - "led test light on", ""); - -U_BOOT_CMD(ledoff, 1, 1, do_led_test_off, - "led test light off", ""); -#endif diff --git a/board/amcc/taishan/showinfo.c b/board/amcc/taishan/showinfo.c deleted file mode 100644 index 53bfdf790b..0000000000 --- a/board/amcc/taishan/showinfo.c +++ /dev/null @@ -1,220 +0,0 @@ -/* - * (C) Copyright 2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <config.h> -#include <common.h> -#include <command.h> -#include <asm/processor.h> -#include <pci.h> - -void show_reset_reg(void) -{ - unsigned long reg; - - /* read clock regsiter */ - printf("===== Display reset and initialize register Start =========\n"); - mfcpr(CPR0_PLLC,reg); - printf("cpr_pllc = %#010lx\n",reg); - - mfcpr(CPR0_PLLD,reg); - printf("cpr_plld = %#010lx\n",reg); - - mfcpr(CPR0_PRIMAD0,reg); - printf("cpr_primad = %#010lx\n",reg); - - mfcpr(CPR0_PRIMBD0,reg); - printf("cpr_primbd = %#010lx\n",reg); - - mfcpr(CPR0_OPBD0,reg); - printf("cpr_opbd = %#010lx\n",reg); - - mfcpr(CPR0_PERD,reg); - printf("cpr_perd = %#010lx\n",reg); - - mfcpr(CPR0_MALD,reg); - printf("cpr_mald = %#010lx\n",reg); - - /* read sdr register */ - mfsdr(SDR0_EBC,reg); - printf("SDR0_EBC = %#010lx\n",reg); - - mfsdr(SDR0_CP440,reg); - printf("SDR0_CP440 = %#010lx\n",reg); - - mfsdr(SDR0_XCR,reg); - printf("SDR0_XCR = %#010lx\n",reg); - - mfsdr(SDR0_XPLLC,reg); - printf("SDR0_XPLLC = %#010lx\n",reg); - - mfsdr(SDR0_XPLLD,reg); - printf("SDR0_XPLLD = %#010lx\n",reg); - - mfsdr(SDR0_PFC0,reg); - printf("SDR0_PFC0 = %#010lx\n",reg); - - mfsdr(SDR0_PFC1,reg); - printf("SDR0_PFC1 = %#010lx\n",reg); - - mfsdr(SDR0_CUST0,reg); - printf("SDR0_CUST0 = %#010lx\n",reg); - - mfsdr(SDR0_CUST1,reg); - printf("SDR0_CUST1 = %#010lx\n",reg); - - mfsdr(SDR0_UART0,reg); - printf("SDR0_UART0 = %#010lx\n",reg); - - mfsdr(SDR0_UART1,reg); - printf("SDR0_UART1 = %#010lx\n",reg); - - printf("===== Display reset and initialize register End =========\n"); -} - -void show_xbridge_info(void) -{ - unsigned long reg; - - printf("PCI-X chip control registers\n"); - mfsdr(SDR0_XCR, reg); - printf("SDR0_XCR = %#010lx\n", reg); - - mfsdr(SDR0_XPLLC, reg); - printf("SDR0_XPLLC = %#010lx\n", reg); - - mfsdr(SDR0_XPLLD, reg); - printf("SDR0_XPLLD = %#010lx\n", reg); - - printf("PCI-X Bridge Configure registers\n"); - printf("PCIL0_VENDID = %#06x\n", in16r(PCIL0_VENDID)); - printf("PCIL0_DEVID = %#06x\n", in16r(PCIL0_DEVID)); - printf("PCIL0_CMD = %#06x\n", in16r(PCIL0_CMD)); - printf("PCIL0_STATUS = %#06x\n", in16r(PCIL0_STATUS)); - printf("PCIL0_REVID = %#04x\n", in8(PCIL0_REVID)); - printf("PCIL0_CACHELS = %#04x\n", in8(PCIL0_CACHELS)); - printf("PCIL0_LATTIM = %#04x\n", in8(PCIL0_LATTIM)); - printf("PCIL0_HDTYPE = %#04x\n", in8(PCIL0_HDTYPE)); - printf("PCIL0_BIST = %#04x\n", in8(PCIL0_BIST)); - - printf("PCIL0_BAR0 = %#010lx\n", in32r(PCIL0_BAR0)); - printf("PCIL0_BAR1 = %#010lx\n", in32r(PCIL0_BAR1)); - printf("PCIL0_BAR2 = %#010lx\n", in32r(PCIL0_BAR2)); - printf("PCIL0_BAR3 = %#010lx\n", in32r(PCIL0_BAR3)); - printf("PCIL0_BAR4 = %#010lx\n", in32r(PCIL0_BAR4)); - printf("PCIL0_BAR5 = %#010lx\n", in32r(PCIL0_BAR5)); - - printf("PCIL0_CISPTR = %#010lx\n", in32r(PCIL0_CISPTR)); - printf("PCIL0_SBSSYSVID = %#010x\n", in16r(PCIL0_SBSYSVID)); - printf("PCIL0_SBSSYSID = %#010x\n", in16r(PCIL0_SBSYSID)); - printf("PCIL0_EROMBA = %#010lx\n", in32r(PCIL0_EROMBA)); - printf("PCIL0_CAP = %#04x\n", in8(PCIL0_CAP)); - printf("PCIL0_INTLN = %#04x\n", in8(PCIL0_INTLN)); - printf("PCIL0_INTPN = %#04x\n", in8(PCIL0_INTPN)); - printf("PCIL0_MINGNT = %#04x\n", in8(PCIL0_MINGNT)); - printf("PCIL0_MAXLTNCY = %#04x\n", in8(PCIL0_MAXLTNCY)); - - printf("PCIL0_BRDGOPT1 = %#010lx\n", in32r(PCIL0_BRDGOPT1)); - printf("PCIL0_BRDGOPT2 = %#010lx\n", in32r(PCIL0_BRDGOPT2)); - - printf("PCIL0_POM0LAL = %#010lx\n", in32r(PCIL0_POM0LAL)); - printf("PCIL0_POM0LAH = %#010lx\n", in32r(PCIL0_POM0LAH)); - printf("PCIL0_POM0SA = %#010lx\n", in32r(PCIL0_POM0SA)); - printf("PCIL0_POM0PCILAL = %#010lx\n", in32r(PCIL0_POM0PCIAL)); - printf("PCIL0_POM0PCILAH = %#010lx\n", in32r(PCIL0_POM0PCIAH)); - printf("PCIL0_POM1LAL = %#010lx\n", in32r(PCIL0_POM1LAL)); - printf("PCIL0_POM1LAH = %#010lx\n", in32r(PCIL0_POM1LAH)); - printf("PCIL0_POM1SA = %#010lx\n", in32r(PCIL0_POM1SA)); - printf("PCIL0_POM1PCILAL = %#010lx\n", in32r(PCIL0_POM1PCIAL)); - printf("PCIL0_POM1PCILAH = %#010lx\n", in32r(PCIL0_POM1PCIAH)); - printf("PCIL0_POM2SA = %#010lx\n", in32r(PCIL0_POM2SA)); - - printf("PCIL0_PIM0SA = %#010lx\n", in32r(PCIL0_PIM0SA)); - printf("PCIL0_PIM0LAL = %#010lx\n", in32r(PCIL0_PIM0LAL)); - printf("PCIL0_PIM0LAH = %#010lx\n", in32r(PCIL0_PIM0LAH)); - printf("PCIL0_PIM1SA = %#010lx\n", in32r(PCIL0_PIM1SA)); - printf("PCIL0_PIM1LAL = %#010lx\n", in32r(PCIL0_PIM1LAL)); - printf("PCIL0_PIM1LAH = %#010lx\n", in32r(PCIL0_PIM1LAH)); - printf("PCIL0_PIM2SA = %#010lx\n", in32r(PCIL0_PIM1SA)); - printf("PCIL0_PIM2LAL = %#010lx\n", in32r(PCIL0_PIM1LAL)); - printf("PCIL0_PIM2LAH = %#010lx\n", in32r(PCIL0_PIM1LAH)); - - printf("PCIL0_XSTS = %#010lx\n", in32r(PCIL0_STS)); -} - -int do_show_xbridge_info(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - show_xbridge_info(); - return 0; -} - -U_BOOT_CMD(xbriinfo, 1, 1, do_show_xbridge_info, - "Show PCIX bridge info", ""); - -#define TAISHAN_PCI_DEV_ID0 0x800 -#define TAISHAN_PCI_DEV_ID1 0x1000 - -void show_pcix_device_info(void) -{ - int ii; - int dev; - u8 capp; - u8 xcapid; - u16 status; - u16 xcommand; - u32 xstatus; - - for (ii = 0; ii < 2; ii++) { - if (ii == 0) - dev = TAISHAN_PCI_DEV_ID0; - else - dev = TAISHAN_PCI_DEV_ID1; - - pci_read_config_word(dev, PCI_STATUS, &status); - if (status & PCI_STATUS_CAP_LIST) { - pci_read_config_byte(dev, PCI_CAPABILITY_LIST, &capp); - - pci_read_config_byte(dev, (int)(capp), &xcapid); - if (xcapid == 0x07) { - pci_read_config_word(dev, (int)(capp + 2), - &xcommand); - pci_read_config_dword(dev, (int)(capp + 4), - &xstatus); - printf("BUS0 dev%d Xcommand=%#06x,Xstatus=%#010x\n", - (ii + 1), xcommand, xstatus); - } else { - printf("BUS0 dev%d PCI-X CAP ID error," - "CAP=%#04x,XCAPID=%#04x\n", - (ii + 1), capp, xcapid); - } - } else { - printf("BUS0 dev%d not found PCI_STATUS_CAP_LIST supporting\n", - ii + 1); - } - } - -} - -int do_show_pcix_device_info(cmd_tbl_t * cmdtp, int flag, int argc, - char * const argv[]) -{ - show_pcix_device_info(); - return 0; -} - -U_BOOT_CMD(xdevinfo, 1, 1, do_show_pcix_device_info, - "Show PCIX Device info", ""); - -extern void show_reset_reg(void); - -int do_show_reset_reg_info(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - show_reset_reg(); - return 0; -} - -U_BOOT_CMD(resetinfo, 1, 1, do_show_reset_reg_info, - "Show Reset REG info", ""); diff --git a/board/amcc/taishan/taishan.c b/board/amcc/taishan/taishan.c deleted file mode 100644 index 5c8d9ec8f1..0000000000 --- a/board/amcc/taishan/taishan.c +++ /dev/null @@ -1,201 +0,0 @@ -/* - * Copyright (C) 2004 PaulReynolds@lhsolutions.com - * - * (C) Copyright 2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/processor.h> -#include <spd_sdram.h> -#include <asm/ppc4xx-emac.h> -#include <netdev.h> - -#ifdef CONFIG_SYS_INIT_SHOW_RESET_REG -void show_reset_reg(void); -#endif - -DECLARE_GLOBAL_DATA_PTR; - -int lcd_init(void); - -int board_early_init_f (void) -{ - unsigned long reg; - volatile unsigned int *GpioOdr; - volatile unsigned int *GpioTcr; - volatile unsigned int *GpioOr; - - /*-------------------------------------------------------------------------+ - | Initialize EBC CONFIG - +-------------------------------------------------------------------------*/ - mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK | - EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK | - EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS | - EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_DEFAULT | - EBC_CFG_PME_DISABLE | EBC_CFG_PR_32); - - /*-------------------------------------------------------------------------+ - | 64MB FLASH. Initialize bank 0 with default values. - +-------------------------------------------------------------------------*/ - mtebc(PB0AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(15) | - EBC_BXAP_BCE_DISABLE | - EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_OEN_ENCODE(1) | - EBC_BXAP_WBN_ENCODE(1) | EBC_BXAP_WBF_ENCODE(1) | - EBC_BXAP_TH_ENCODE(3) | EBC_BXAP_RE_DISABLED | - EBC_BXAP_BEM_WRITEONLY | - EBC_BXAP_PEN_DISABLED); - mtebc(PB0CR, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | - EBC_BXCR_BS_64MB | EBC_BXCR_BU_RW|EBC_BXCR_BW_32BIT); - - /*-------------------------------------------------------------------------+ - | FPGA. Initialize bank 1 with default values. - +-------------------------------------------------------------------------*/ - mtebc(PB1AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(5) | - EBC_BXAP_BCE_DISABLE | - EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_OEN_ENCODE(1) | - EBC_BXAP_WBN_ENCODE(1) | EBC_BXAP_WBF_ENCODE(1) | - EBC_BXAP_TH_ENCODE(3) | EBC_BXAP_RE_DISABLED | - EBC_BXAP_BEM_WRITEONLY | - EBC_BXAP_PEN_DISABLED); - mtebc(PB1CR, EBC_BXCR_BAS_ENCODE(0x41000000) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT); - - /*-------------------------------------------------------------------------+ - | LCM. Initialize bank 2 with default values. - +-------------------------------------------------------------------------*/ - mtebc(PB2AP, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(64) | - EBC_BXAP_BCE_DISABLE | - EBC_BXAP_CSN_ENCODE(3) | EBC_BXAP_OEN_ENCODE(3) | - EBC_BXAP_WBN_ENCODE(3) | EBC_BXAP_WBF_ENCODE(3) | - EBC_BXAP_TH_ENCODE(7) | EBC_BXAP_RE_DISABLED | - EBC_BXAP_BEM_WRITEONLY | - EBC_BXAP_PEN_DISABLED); - mtebc(PB2CR, EBC_BXCR_BAS_ENCODE(0x42000000) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT); - - /*-------------------------------------------------------------------------+ - | TMP. Initialize bank 3 with default values. - +-------------------------------------------------------------------------*/ - mtebc(PB3AP, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(128) | - EBC_BXAP_BCE_DISABLE | - EBC_BXAP_CSN_ENCODE(3) | EBC_BXAP_OEN_ENCODE(3) | - EBC_BXAP_WBN_ENCODE(3) | EBC_BXAP_WBF_ENCODE(3) | - EBC_BXAP_TH_ENCODE(7) | EBC_BXAP_RE_DISABLED | - EBC_BXAP_BEM_WRITEONLY | - EBC_BXAP_PEN_DISABLED); - mtebc(PB3CR, EBC_BXCR_BAS_ENCODE(0x48000000) | - EBC_BXCR_BS_64MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); - - /*-------------------------------------------------------------------------+ - | Connector 4~7. Initialize bank 3~ 7 with default values. - +-------------------------------------------------------------------------*/ - mtebc(PB4AP,0); - mtebc(PB4CR,0); - mtebc(PB5AP,0); - mtebc(PB5CR,0); - mtebc(PB6AP,0); - mtebc(PB6CR,0); - mtebc(PB7AP,0); - mtebc(PB7CR,0); - - /*-------------------------------------------------------------------- - * Setup the interrupt controller polarities, triggers, etc. - *-------------------------------------------------------------------*/ - /* - * Because of the interrupt handling rework to handle 440GX interrupts - * with the common code, we needed to change names of the UIC registers. - * Here the new relationship: - * - * U-Boot name 440GX name - * ----------------------- - * UIC0 UICB0 - * UIC1 UIC0 - * UIC2 UIC1 - * UIC3 UIC2 - */ - mtdcr (UIC1SR, 0xffffffff); /* clear all */ - mtdcr (UIC1ER, 0x00000000); /* disable all */ - mtdcr (UIC1CR, 0x00000009); /* SMI & UIC1 crit are critical */ - mtdcr (UIC1PR, 0xfffffe13); /* per ref-board manual */ - mtdcr (UIC1TR, 0x01c00008); /* per ref-board manual */ - mtdcr (UIC1VR, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (UIC1SR, 0xffffffff); /* clear all */ - - mtdcr (UIC2SR, 0xffffffff); /* clear all */ - mtdcr (UIC2ER, 0x00000000); /* disable all */ - mtdcr (UIC2CR, 0x00000000); /* all non-critical */ - mtdcr (UIC2PR, 0xffffe0ff); /* per ref-board manual */ - mtdcr (UIC2TR, 0x00ffc000); /* per ref-board manual */ - mtdcr (UIC2VR, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (UIC2SR, 0xffffffff); /* clear all */ - - mtdcr (UIC3SR, 0xffffffff); /* clear all */ - mtdcr (UIC3ER, 0x00000000); /* disable all */ - mtdcr (UIC3CR, 0x00000000); /* all non-critical */ - mtdcr (UIC3PR, 0xffffffff); /* per ref-board manual */ - mtdcr (UIC3TR, 0x00ff8c0f); /* per ref-board manual */ - mtdcr (UIC3VR, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (UIC3SR, 0xffffffff); /* clear all */ - - mtdcr (UIC0SR, 0xfc000000); /* clear all */ - mtdcr (UIC0ER, 0x00000000); /* disable all */ - mtdcr (UIC0CR, 0x00000000); /* all non-critical */ - mtdcr (UIC0PR, 0xfc000000); /* */ - mtdcr (UIC0TR, 0x00000000); /* */ - mtdcr (UIC0VR, 0x00000001); /* */ - - /* Enable two GPIO 10~11 and TraceA signal */ - mfsdr(SDR0_PFC0,reg); - reg |= 0x00300000; - mtsdr(SDR0_PFC0,reg); - - mfsdr(SDR0_PFC1,reg); - reg |= 0x00100000; - mtsdr(SDR0_PFC1,reg); - - /* Set GPIO 10 and 11 as output */ - GpioOdr = (volatile unsigned int*)(CONFIG_SYS_PERIPHERAL_BASE+0x718); - GpioTcr = (volatile unsigned int*)(CONFIG_SYS_PERIPHERAL_BASE+0x704); - GpioOr = (volatile unsigned int*)(CONFIG_SYS_PERIPHERAL_BASE+0x700); - - *GpioOdr &= ~(0x00300000); - *GpioTcr |= 0x00300000; - *GpioOr |= 0x00300000; - - return 0; -} - -int misc_init_r(void) -{ - lcd_init(); - - return 0; -} - -int checkboard (void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - printf ("Board: Taishan - AMCC PPC440GX Evaluation Board"); - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc ('\n'); - -#ifdef CONFIG_SYS_INIT_SHOW_RESET_REG - show_reset_reg(); -#endif - - return (0); -} - -int board_eth_init(bd_t *bis) -{ - cpu_eth_init(bis); - return pci_eth_init(bis); -} diff --git a/board/amcc/taishan/update.c b/board/amcc/taishan/update.c deleted file mode 100644 index 273898929a..0000000000 --- a/board/amcc/taishan/update.c +++ /dev/null @@ -1,62 +0,0 @@ -/* - * (C) Copyright 2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <config.h> -#include <common.h> -#include <command.h> -#include <asm/processor.h> -#include <i2c.h> - -#if defined(CONFIG_TAISHAN) - -const uchar bootstrap_buf[16] = { - 0x86, - 0x78, - 0xc1, - 0xa6, - 0x09, - 0x67, - 0x04, - 0x63, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00 -}; - -static int update_boot_eeprom(void) -{ - ulong len = 0x10; - uchar chip = CONFIG_SYS_BOOTSTRAP_IIC_ADDR; - uchar *pbuf = (uchar *)bootstrap_buf; - int ii, jj; - - for (ii = 0; ii < len; ii++) { - if (i2c_write(chip, ii, 1, &pbuf[ii], 1) != 0) { - printf("i2c_write failed\n"); - return -1; - } - - /* wait 10ms */ - for (jj = 0; jj < 10; jj++) - udelay(1000); - } - return 0; -} - -int do_update_boot_eeprom(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - return update_boot_eeprom(); -} - -U_BOOT_CMD(update_boot_eeprom, 1, 1, do_update_boot_eeprom, - "update bootstrap eeprom content", ""); -#endif diff --git a/configs/ebony_defconfig b/configs/ebony_defconfig deleted file mode 100644 index db93555b9e..0000000000 --- a/configs/ebony_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_4xx=y -CONFIG_TARGET_EBONY=y diff --git a/configs/ocotea_defconfig b/configs/ocotea_defconfig deleted file mode 100644 index 34518cd457..0000000000 --- a/configs/ocotea_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_4xx=y -CONFIG_TARGET_OCOTEA=y diff --git a/configs/taihu_defconfig b/configs/taihu_defconfig deleted file mode 100644 index ac83725130..0000000000 --- a/configs/taihu_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_4xx=y -CONFIG_TARGET_TAIHU=y diff --git a/configs/taishan_defconfig b/configs/taishan_defconfig deleted file mode 100644 index e956c6f856..0000000000 --- a/configs/taishan_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_4xx=y -CONFIG_TARGET_TAISHAN=y diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 2760f60f6d..cddaff6938 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -12,6 +12,10 @@ The list should be sorted in reverse chronological order. Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +ocotea powerpc ppc4xx - - Stefan Roese <sr@denx.de> +taishan powerpc ppc4xx - - Stefan Roese <sr@denx.de> +ebony powerpc ppc4xx - - Stefan Roese <sr@denx.de> +taihu powerpc ppc4xx - - John Otken <jotken@softadvances.com> lcd4_lwmon5 powerpc ppc4xx b6b5e394 2015-10-02 Stefan Roese <sr@denx.de> da830evm arm arm926ejs d7e8b2b9 2015-09-12 Nick Thompson <nick.thompson@gefanuc.com> wireless_space arm arm926ejs b352182a 2015-09-12 Albert ARIBAUD <albert.u.boot@aribaud.net> diff --git a/include/configs/ebony.h b/include/configs/ebony.h deleted file mode 100644 index 3f0ad69738..0000000000 --- a/include/configs/ebony.h +++ /dev/null @@ -1,174 +0,0 @@ -/* - * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/************************************************************************ - * board/config_EBONY.h - configuration for AMCC 440GP Ref (Ebony) - ***********************************************************************/ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/*----------------------------------------------------------------------- - * High Level Configuration Options - *----------------------------------------------------------------------*/ -#define CONFIG_EBONY 1 /* Board is ebony */ -#define CONFIG_440GP 1 /* Specifc GP support */ -#define CONFIG_440 1 /* ... PPC440 family */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ -#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ - -#define CONFIG_SYS_TEXT_BASE 0xFFFC0000 - -/* - * Include common defines/options for all AMCC eval boards - */ -#define CONFIG_HOSTNAME ebony -#include "amcc-common.h" - -/* - * Define here the location of the environment variables (FLASH or NVRAM). - * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only - * supported for backward compatibility. - */ -#if 1 -#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ -#else -#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ -#endif - -/*----------------------------------------------------------------------- - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */ -#define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH */ -#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ -#define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */ -#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ - -#define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000) -#define CONFIG_SYS_FPGA_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08300000) - -/*----------------------------------------------------------------------- - * Initial RAM & stack pointer (placed in internal SRAM) - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Serial Port - *----------------------------------------------------------------------*/ -#define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#define CONFIG_SYS_EXT_SERIAL_CLOCK (1843200 * 6) /* Ext clk @ 11.059 MHz */ - -/*----------------------------------------------------------------------- - * NVRAM/RTC - * - * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located. - * The DS1743 code assumes this condition (i.e. -- it assumes the base - * address for the RTC registers is: - * - * CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE - * - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs */ -#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */ - -#ifdef CONFIG_ENV_IS_IN_NVRAM -#define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */ -#define CONFIG_ENV_ADDR \ - (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) -#endif /* CONFIG_ENV_IS_IN_NVRAM */ - -/*----------------------------------------------------------------------- - * FLASH related - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_MAX_FLASH_BANKS 3 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 32 /* sectors per device */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -#define CONFIG_SYS_FLASH_ADDR0 0x5555 -#define CONFIG_SYS_FLASH_ADDR1 0x2aaa -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char - -#ifdef CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) -#endif /* CONFIG_ENV_IS_IN_FLASH */ - -/*----------------------------------------------------------------------- - * DDR SDRAM - *----------------------------------------------------------------------*/ -#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */ -#define SPD_EEPROM_ADDRESS {0x53,0x52} /* SPD i2c spd addresses */ -#define CONFIG_PROG_SDRAM_TLB 1 /* setup SDRAM TLB's dynamically*/ - -/*----------------------------------------------------------------------- - * I2C - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 - -#define CONFIG_SYS_I2C_MULTI_EEPROMS -#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1) -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 - -/* - * Default environment variables - */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_AMCC_DEF_ENV \ - CONFIG_AMCC_DEF_ENV_POWERPC \ - CONFIG_AMCC_DEF_ENV_PPC_OLD \ - CONFIG_AMCC_DEF_ENV_NOR_UPD \ - "kernel_addr=ff800000\0" \ - "ramdisk_addr=ff810000\0" \ - "" - -#define CONFIG_PHY_ADDR 8 /* PHY address */ -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#define CONFIG_PHY1_ADDR 9 /* EMAC1 PHY address */ - -/* - * Commands additional to the ones defined in amcc-common.h - */ -#define CONFIG_CMD_DATE -#define CONFIG_CMD_PCI -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_SNTP - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -/* General PCI */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */ - -/* Board-specific PCI */ -#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */ - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/ocotea.h b/include/configs/ocotea.h deleted file mode 100644 index 4ff2f05c88..0000000000 --- a/include/configs/ocotea.h +++ /dev/null @@ -1,194 +0,0 @@ -/* - * (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com> - * - * (C) Copyright 2005 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/************************************************************************ - * 1 March 2004 Travis B. Sawyer <tsawyer@sandburst.com> - * Adapted to current Das U-Boot source - ***********************************************************************/ - - -/************************************************************************ - * OCOTEA.h - configuration for AMCC 440GX Ref (Ocotea) - ***********************************************************************/ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/*----------------------------------------------------------------------- - * High Level Configuration Options - *----------------------------------------------------------------------*/ -#define CONFIG_OCOTEA 1 /* Board is ebony */ -#define CONFIG_440GX 1 /* Specifc GX support */ -#define CONFIG_440 1 /* ... PPC440 family */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ -#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ - -#define CONFIG_SYS_TEXT_BASE 0xFFFC0000 - -/* - * Include common defines/options for all AMCC eval boards - */ -#define CONFIG_HOSTNAME ocotea -#include "amcc-common.h" - -/*----------------------------------------------------------------------- - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH */ -#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ -#define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */ -#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ - -#define CONFIG_SYS_FPGA_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08300000) -#define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000) - -/*----------------------------------------------------------------------- - * Initial RAM & stack pointer (placed in internal SRAM) - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_TEMP_STACK_OCM 1 -#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4) - -/*----------------------------------------------------------------------- - * Serial Port - *----------------------------------------------------------------------*/ -#define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#define CONFIG_SYS_EXT_SERIAL_CLOCK (1843200 * 6) /* Ext clk @ 11.059 MHz */ - -/*----------------------------------------------------------------------- - * Environment - *----------------------------------------------------------------------*/ -/* - * Define here the location of the environment variables (FLASH or NVRAM). - * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only - * supported for backward compatibility. - */ -#if 1 -#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ -#else -#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ -#endif - - -/*----------------------------------------------------------------------- - * NVRAM/RTC - * - * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located. - * The DS1743 code assumes this condition (i.e. -- it assumes the base - * address for the RTC registers is: - * - * CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE - * - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs */ -#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */ - -#ifdef CONFIG_ENV_IS_IN_NVRAM -#define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */ -#define CONFIG_ENV_ADDR \ - (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) -#endif /* CONFIG_ENV_IS_IN_NVRAM */ - -/*----------------------------------------------------------------------- - * FLASH related - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_MAX_FLASH_BANKS 3 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ - -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_SYS_FLASH_ADDR0 0x5555 -#define CONFIG_SYS_FLASH_ADDR1 0x2aaa -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char - -#ifdef CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) -#endif /* CONFIG_ENV_IS_IN_FLASH */ - -/*----------------------------------------------------------------------- - * DDR SDRAM - *----------------------------------------------------------------------*/ -#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */ -#define SPD_EEPROM_ADDRESS {0x53,0x52} /* SPD i2c spd addresses */ -#define CONFIG_PROG_SDRAM_TLB 1 /* setup SDRAM TLB's dynamically*/ - -/*----------------------------------------------------------------------- - * I2C - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 - -#define CONFIG_SYS_I2C_MULTI_EEPROMS -#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1) -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 - -/* - * Default environment variables - */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_AMCC_DEF_ENV \ - CONFIG_AMCC_DEF_ENV_PPC \ - CONFIG_AMCC_DEF_ENV_NOR_UPD \ - "kernel_addr=fff00000\0" \ - "ramdisk_addr=fff10000\0" \ - "" - -#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ -#define CONFIG_PHY1_ADDR 2 -#define CONFIG_PHY2_ADDR 0x10 -#define CONFIG_PHY3_ADDR 0x18 -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#define CONFIG_HAS_ETH2 -#define CONFIG_HAS_ETH3 -#define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */ -#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ -#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ -#define CONFIG_PHY_RESET_DELAY 1000 - -/* - * Commands additional to the ones defined in amcc-common.h - */ -#define CONFIG_CMD_DATE -#define CONFIG_CMD_PCI -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_SNTP - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -/* General PCI */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */ - -/* Board-specific PCI */ -#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */ - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/taihu.h b/include/configs/taihu.h deleted file mode 100644 index 5c0ce7a2e4..0000000000 --- a/include/configs/taihu.h +++ /dev/null @@ -1,307 +0,0 @@ -/* - * (C) Copyright 2000-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2005-2007 - * Beijing UD Technology Co., Ltd., taihusupport@amcc.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - - -#define CONFIG_405EP 1 /* this is a PPC405 CPU */ -#define CONFIG_TAIHU 1 /* on a taihu board */ - -#define CONFIG_SYS_TEXT_BASE 0xFFFC0000 - -/* - * Include common defines/options for all AMCC eval boards - */ -#define CONFIG_HOSTNAME taihu -#include "amcc-common.h" - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f */ - -#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ - -#define CONFIG_NO_SERIAL_EEPROM - -/*----------------------------------------------------------------------------*/ -#ifdef CONFIG_NO_SERIAL_EEPROM - -/* -!------------------------------------------------------------------------------- -! PLL settings for 333MHz CPU, 111MHz PLB/SDRAM, 55MHz EBC, 33MHz PCI, -! assuming a 33MHz input clock to the 405EP from the C9531. -!------------------------------------------------------------------------------- -*/ -#define PLLMR0_333_111_55_37 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ - PLL_MALDIV_1 | PLL_PCIDIV_3) -#define PLLMR1_333_111_55_37 (PLL_FBKDIV_10 | \ - PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) -#define PLLMR0_333_111_55_111 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ - PLL_MALDIV_1 | PLL_PCIDIV_1) -#define PLLMR1_333_111_55_111 (PLL_FBKDIV_10 | \ - PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) - -#define PLLMR0_DEFAULT PLLMR0_333_111_55_37 -#define PLLMR1_DEFAULT PLLMR1_333_111_55_37 -#define PLLMR0_DEFAULT_PCI66 PLLMR0_333_111_55_111 -#define PLLMR1_DEFAULT_PCI66 PLLMR1_333_111_55_111 - -#endif -/*----------------------------------------------------------------------------*/ - -#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ - -/* - * Default environment variables - */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_AMCC_DEF_ENV \ - CONFIG_AMCC_DEF_ENV_PPC \ - CONFIG_AMCC_DEF_ENV_NOR_UPD \ - "kernel_addr=FC000000\0" \ - "ramdisk_addr=FC180000\0" \ - "" - -#define CONFIG_PHY_ADDR 0x14 /* PHY address */ -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#define CONFIG_PHY1_ADDR 0x10 /* EMAC1 PHY address */ -#define CONFIG_PHY_RESET 1 - -/* - * Commands additional to the ones defined in amcc-common.h - */ -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_PCI -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_SPI - -#undef CONFIG_SPD_EEPROM /* use SPD EEPROM for setup */ -#define CONFIG_SYS_SDRAM_SIZE_PER_BANK 0x04000000 /* 64MB */ -#define CONFIG_SYS_SDRAM_BANKS 2 - -/* - * SDRAM configuration (please see cpu/ppc/sdram.[ch]) - */ -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ -#define CONFIG_SDRAM_BANK1 1 /* init onboard SDRAM bank 1 */ - -/* SDRAM timings used in datasheet */ -#define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */ -#define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */ -#define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE command period */ -#define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */ -#define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */ - -/* - * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1. - * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31. - * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value. - * The Linux BASE_BAUD define should match this configuration. - * baseBaud = cpuClock/(uartDivisor*16) - * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock, - * set Linux BASE_BAUD to 403200. - */ -#define CONFIG_CONS_INDEX 2 /* Use UART1 */ -#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ -#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ -#define CONFIG_SYS_BASE_BAUD 691200 - -/*----------------------------------------------------------------------- - * I2C stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 - -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* avoid i2c probe hangup (?) */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */ - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C boot EEPROM (24C02W) */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ - -#define CONFIG_SOFT_SPI -#define SPI_SCL spi_scl -#define SPI_SDA spi_sda -#define SPI_READ spi_read() -#define SPI_DELAY udelay(2) -#ifndef __ASSEMBLY__ -void spi_scl(int); -void spi_sda(int); -unsigned char spi_read(void); -#endif - -/* standard dtt sensor configuration */ -#define CONFIG_DTT_DS1775 1 -#define CONFIG_DTT_SENSORS { 0 } -#define CONFIG_SYS_I2C_DTT_ADDR 0x49 - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ -#define CONFIG_SYS_PCI_CLASSCODE 0x0600 /* PCI Class Code: bridge/host */ -#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ -#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */ -#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */ -#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ -#define CONFIG_EEPRO100 1 - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - */ -#define CONFIG_SYS_FLASH_BASE 0xFFE00000 - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_SYS_FLASH_ADDR0 0x555 -#define CONFIG_SYS_FLASH_ADDR1 0x2aa -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short - -#ifdef CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) -#endif /* CONFIG_ENV_IS_IN_FLASH */ - -/*----------------------------------------------------------------------- - * NVRAM organization - */ -#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */ -#define CONFIG_SYS_NVRAM_SIZE 0x1ff8 /* NVRAM size */ - -#ifdef CONFIG_ENV_IS_IN_NVRAM -#define CONFIG_ENV_SIZE 0x0ff8 /* Size of Environment vars */ -#define CONFIG_ENV_ADDR \ - (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env*/ -#endif - -/*----------------------------------------------------------------------- - * PPC405 GPIO Configuration - */ -#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 */ \ -{ \ -/* GPIO Core 0 */ \ -{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast SPI CS */ \ -{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \ -{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \ -{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \ -{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \ -{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO5 TS3 */ \ -{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \ -{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO7 TS5 */ \ -{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \ -{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \ -{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \ -{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \ -{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \ -{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \ -{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 SPI SCLK */ \ -{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 SPI DI */ \ -{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 SPI DO */ \ -{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 PCI INTA */ \ -{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 PCI INTB */ \ -{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 PCI INTC */ \ -{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 PCI INTD */ \ -{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 USB */ \ -{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 EBC */ \ -{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 unused */ \ -{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD UART1 */ \ -{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \ -{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \ -{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \ -{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx UART0 */ \ -{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \ -{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 User LED1 */ \ -{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 User LED2 */ \ -} \ -} - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0xFC000000 /* FLASH bank #1 */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in data cache) - */ -/* use on chip memory (OCM) for temperary stack until sdram is tested */ -#define CONFIG_SYS_TEMP_STACK_OCM 1 - -/* On Chip Memory location */ -#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 -#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ - -/* Memory Bank 0 (Flash/SRAM) initialization */ -#define CONFIG_SYS_EBC_PB0AP 0x03815600 -#define CONFIG_SYS_EBC_PB0CR 0xFFE3A000 /* BAS=0xFFE,BS=2MB,BU=R/W,BW=16bit */ - -/* Memory Bank 1 (NVRAM/RTC) initialization */ -#define CONFIG_SYS_EBC_PB1AP 0x05815600 -#define CONFIG_SYS_EBC_PB1CR 0xFC0BA000 /* BAS=0xFc0,BS=32MB,BU=R/W,BW=16bit */ - -/* Memory Bank 2 (USB device) initialization */ -#define CONFIG_SYS_EBC_PB2AP 0x03016600 -#define CONFIG_SYS_EBC_PB2CR 0x50018000 /* BAS=0x500,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 3 (LCM and D-flip-flop) initialization */ -#define CONFIG_SYS_EBC_PB3AP 0x158FF600 -#define CONFIG_SYS_EBC_PB3CR 0x50118000 /* BAS=0x501,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 4 (not install) initialization */ -#define CONFIG_SYS_EBC_PB4AP 0x158FF600 -#define CONFIG_SYS_EBC_PB4CR 0x5021A000 - -#define CPLD_REG0_ADDR 0x50100000 -#define CPLD_REG1_ADDR 0x50100001 - -#endif /* __CONFIG_H */ diff --git a/include/configs/taishan.h b/include/configs/taishan.h deleted file mode 100644 index 3d5c351b1a..0000000000 --- a/include/configs/taishan.h +++ /dev/null @@ -1,193 +0,0 @@ -/* - * (C) Copyright 2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/************************************************************************ - * TAISHAN.h - configuration for AMCC 440GX Ref - ***********************************************************************/ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/*----------------------------------------------------------------------- - * High Level Configuration Options - *----------------------------------------------------------------------*/ -#define CONFIG_TAISHAN 1 /* Board is taishan */ -#define CONFIG_440GX 1 /* Specifc GX support */ -#define CONFIG_440 1 /* ... PPC440 family */ -#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ - -#define CONFIG_SYS_TEXT_BASE 0xFFFC0000 - -/* - * Include common defines/options for all AMCC eval boards - */ -#define CONFIG_HOSTNAME taishan -#define CONFIG_USE_TTY ttyS1 -#include "amcc-common.h" - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ -#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ - -/*----------------------------------------------------------------------- - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of FLASH */ -#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ -#define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */ -#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ - -#define CONFIG_SYS_EBC0_FLASH_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_EBC1_FPGA_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x01000000) -#define CONFIG_SYS_EBC2_LCM_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x02000000) -#define CONFIG_SYS_EBC3_CONN_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000) - -#define CONFIG_SYS_GPIO_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700) - -/*----------------------------------------------------------------------- - * Initial RAM & stack pointer (placed in internal SRAM) - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_TEMP_STACK_OCM 1 -#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM*/ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4) - -/*----------------------------------------------------------------------- - * Serial Port - *----------------------------------------------------------------------*/ -#define CONFIG_CONS_INDEX 2 /* Use UART1 */ -#define CONFIG_SYS_EXT_SERIAL_CLOCK (1843200 * 6) /* Ext clk @ 11.059 MHz */ - -/*----------------------------------------------------------------------- - * Environment - *----------------------------------------------------------------------*/ -#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ - -/*----------------------------------------------------------------------- - * FLASH related - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ - -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ - -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -/*----------------------------------------------------------------------- - * E2PROM bootstrap configure value - *----------------------------------------------------------------------*/ - -/* - * 800/133/66 - * IIC 0~15: 86 78 11 6a 61 A7 04 62 00 00 00 00 00 00 00 00 - */ - -/* - * 800/160/80 - * IIC 0~15: 86 78 c1 a6 09 67 04 63 00 00 00 00 00 00 00 00 - */ - -/*----------------------------------------------------------------------- - * DDR SDRAM - *----------------------------------------------------------------------*/ -#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */ -#define CONFIG_SDRAM_BANK0 1 /* init onboard DDR SDRAM bank 0 */ -#define CONFIG_SYS_SDRAM0_TR0 0xC10A401A -#undef CONFIG_SDRAM_ECC /* enable ECC support */ - -/*----------------------------------------------------------------------- - * I2C - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 - -#undef CONFIG_SYS_I2C_MULTI_EEPROMS -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 - -#define CONFIG_SYS_BOOTSTRAP_IIC_ADDR 0x50 - -/* I2C SYSMON (LM75, AD7414 is almost compatible) */ -#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ -#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ -#define CONFIG_SYS_DTT_MAX_TEMP 70 -#define CONFIG_SYS_DTT_LOW_TEMP -30 -#define CONFIG_SYS_DTT_HYSTERESIS 3 - -/* - * Default environment variables - */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_AMCC_DEF_ENV \ - CONFIG_AMCC_DEF_ENV_POWERPC \ - CONFIG_AMCC_DEF_ENV_PPC_OLD \ - CONFIG_AMCC_DEF_ENV_NOR_UPD \ - "kernel_addr=fc000000\0" \ - "ramdisk_addr=fc180000\0" \ - "kozio=bootm 0xffe00000\0" \ - "" - -/*----------------------------------------------------------------------- - * Networking - *----------------------------------------------------------------------*/ -#define CONFIG_EMAC_NR_START 2 /* start with EMAC 2 (skip 0&1) */ -#define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */ -#define CONFIG_PHY1_ADDR 0xff /* no phy on EMAC1 */ -#define CONFIG_PHY2_ADDR 0x1 -#define CONFIG_PHY3_ADDR 0x3 -#define CONFIG_ET1011C_PHY 1 -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#define CONFIG_HAS_ETH2 -#define CONFIG_HAS_ETH3 -#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ -#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ -#define CONFIG_PHY_RESET_DELAY 1000 - -/* - * Commands additional to the ones defined in amcc-common.h - */ -#define CONFIG_CMD_DTT -#define CONFIG_CMD_PCI - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -/* General PCI */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_EEPRO100 1 /* include PCI EEPRO100 */ -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */ - -/* Board-specific PCI */ -#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */ - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ - -#endif /* __CONFIG_H */ |
