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| author | Stefan Roese <sr@denx.de> | 2007-07-31 08:37:01 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2007-07-31 08:37:01 +0200 |
| commit | ea9f6bce383cc9fbcdee28b5836109b1a6dba574 (patch) | |
| tree | d9059c7f3842f92c0bcf047b86fab4c44863ea78 /post | |
| parent | 27a528fb41433c4c1e2b5d6bd3fd8d78606fc724 (diff) | |
| download | talos-obmc-uboot-ea9f6bce383cc9fbcdee28b5836109b1a6dba574.tar.gz talos-obmc-uboot-ea9f6bce383cc9fbcdee28b5836109b1a6dba574.zip | |
ppc4xx: Update 440EPx lwmon5 board support
- Clear ECC status regs after ECC POST test
- Set dcbz for ECC generation with caches enabled as default
- Code cleanup
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'post')
| -rw-r--r-- | post/board/lwmon5/ecc.c | 12 | ||||
| -rw-r--r-- | post/cpu/ppc4xx/fpu.c | 2 |
2 files changed, 12 insertions, 2 deletions
diff --git a/post/board/lwmon5/ecc.c b/post/board/lwmon5/ecc.c index 7f04f9abed..3fa3ba6243 100644 --- a/post/board/lwmon5/ecc.c +++ b/post/board/lwmon5/ecc.c @@ -236,7 +236,6 @@ int ecc_post_test (int flags) mfsdram(DDR0_00, value); mtsdram(DDR0_00, value | DDR0_00_INT_ACK_ALL); - /* enable full support of ECC */ mfsdram(DDR0_22, value); mtsdram(DDR0_22, (value &~ DDR0_22_CTRL_RAW_MASK) @@ -247,6 +246,17 @@ int ecc_post_test (int flags) if (ret) break; } + + /* clear error status */ + mfsdram(DDR0_00, value); + mtsdram(DDR0_00, value | DDR0_00_INT_ACK_ALL); + + /* + * Clear possible errors resulting from ECC testing. + * If not done, then we could get an interrupt later on when + * exceptions are enabled. + */ + set_mcsr(get_mcsr()); #endif return ret; diff --git a/post/cpu/ppc4xx/fpu.c b/post/cpu/ppc4xx/fpu.c index 27e9ed01af..0c26fe00e4 100644 --- a/post/cpu/ppc4xx/fpu.c +++ b/post/cpu/ppc4xx/fpu.c @@ -29,8 +29,8 @@ #if defined(CONFIG_440EP) || \ defined(CONFIG_440EPX) -#include <ppc4xx.h> #include <asm/processor.h> +#include <ppc4xx.h> int fpu_status(void) |
