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| author | Peng Fan <peng.fan@nxp.com> | 2016-05-04 15:27:50 +0800 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2016-05-06 10:43:39 -0400 |
| commit | ad7af5d7e4caf49581c7403d5a8edc0f11a5f652 (patch) | |
| tree | 8c9506f950d5f409413970d08f7b697e65c961fe /lib/rand.c | |
| parent | daa69f5f5dba48406836b1879434fc4af4bb7df7 (diff) | |
| download | talos-obmc-uboot-ad7af5d7e4caf49581c7403d5a8edc0f11a5f652.tar.gz talos-obmc-uboot-ad7af5d7e4caf49581c7403d5a8edc0f11a5f652.zip | |
imx6: cache: disable L2 before touching Auxiliary Control Register
According PL310 TRM, Auxiliary Control Register
"
The register must be written to using a secure access, and it can be
read using either a secure or a NS access. If you write to this register
with a NS access, it results in a write response with a DECERR response,
and the register is not updated. Writing to this register with the L2
cache enabled, that is, bit[0] of L2 Control Register set to 1,
results in a SLVERR.
"
So If L2 cache is already enabled by ROM, chaning value of ACR
will cause SLVERR and uboot hang.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Diffstat (limited to 'lib/rand.c')
0 files changed, 0 insertions, 0 deletions
