Merge branch 'origin' into kconfig-for-1.3.1

Conflicts:

	drivers/Makefile

9 files changed, 118 insertions, 70 deletions

diff --git a/include/asm-m68k/immap_5329.h b/include/asm-m68k/immap_5329.h
index 2a3980c130..271c27655b 100644
--- a/include/asm-m68k/immap_5329.h
+++ b/include/asm-m68k/immap_5329.h
@@ -57,7 +57,8 @@
 #define MMAP_PWM	0xFC090000
 #define MMAP_EPORT	0xFC094000
 #define MMAP_WDOG	0xFC098000
-#define MMAP_CCM	0xFC0A0000
+#define MMAP_RCM	0xFC0A0000
+#define MMAP_CCM	0xFC0A0004
 #define MMAP_GPIO	0xFC0A4000
 #define MMAP_RTC	0xFC0A8000
 #define MMAP_LCDC	0xFC0AC000
@@ -479,20 +480,22 @@ typedef struct wdog_ctrl {
 
 /*Chip configuration module registers */
 typedef struct ccm_ctrl {
-	u8 rstctrl;		/* 0x00 Reset Controller register */
-	u8 rststat;		/* 0x01 Reset Status register */
-	u16 res1;		/* 0x02 - 0x03 */
-	u16 ccr;		/* 0x04 Chip configuration register */
-	u16 res2;		/* 0x06 */
-	u16 rcon;		/* 0x08 Rreset configuration register */
-	u16 cir;		/* 0x0A Chip identification register */
-	u32 res3;		/* 0x0C */
-	u16 misccr;		/* 0x10 Miscellaneous control register */
-	u16 cdr;		/* 0x12 Clock divider register */
-	u16 uhcsr;		/* 0x14 USB Host controller status register */
-	u16 uocsr;		/* 0x16 USB On-the-Go Controller Status Register */
+	u16 ccr;		/* 0x00 Chip configuration register */
+	u16 res2;		/* 0x02 */
+	u16 rcon;		/* 0x04 Rreset configuration register */
+	u16 cir;		/* 0x06 Chip identification register */
+	u32 res3;		/* 0x08 */
+	u16 misccr;		/* 0x0A Miscellaneous control register */
+	u16 cdr;		/* 0x0C Clock divider register */
+	u16 uhcsr;		/* 0x10 USB Host controller status register */
+	u16 uocsr;		/* 0x12 USB On-the-Go Controller Status Reg */
 } ccm_t;
 
+typedef struct rcm {
+	u8 rcr;
+	u8 rsr;
+} rcm_t;
+
 /* GPIO port registers */
 typedef struct gpio_ctrl {
 	/* Port Output Data Registers */
diff --git a/include/asm-m68k/m5329.h b/include/asm-m68k/m5329.h
index cd69fb0b5a..3f056511cb 100644
--- a/include/asm-m68k/m5329.h
+++ b/include/asm-m68k/m5329.h
@@ -246,6 +246,21 @@
 #define CSCR_BSTW			(0x00000008)
 
 /*********************************************************************
+* Reset Controller Module (RCM)
+*********************************************************************/
+
+/* Bit definitions and macros for RCR */
+#define RCM_RCR_FRCRSTOUT		(0x40)
+#define RCM_RCR_SOFTRST			(0x80)
+
+/* Bit definitions and macros for RSR */
+#define RCM_RSR_LOL			(0x01)
+#define RCM_RSR_WDR_CORE		(0x02)
+#define RCM_RSR_EXT			(0x04)
+#define RCM_RSR_POR			(0x08)
+#define RCM_RSR_SOFT			(0x20)
+
+/*********************************************************************
 * FlexCAN Module (CAN)
 *********************************************************************/
 /* Bit definitions and macros for CAN_CANMCR */
diff --git a/include/asm-m68k/m5445x.h b/include/asm-m68k/m5445x.h
index 8b886b0b60..b2bfb69264 100644
--- a/include/asm-m68k/m5445x.h
+++ b/include/asm-m68k/m5445x.h
@@ -792,8 +792,8 @@
 #define GPIO_PAR_FEC_FEC0_MASK		(0xF8)
 #define GPIO_PAR_FEC_FEC0_MII		(0x07)
 #define GPIO_PAR_FEC_FEC0_RMII_GPIO	(0x03)
-#define GPIO_PAR_FEC_FEC0_RMII_ATA	(0x02)
-#define GPIO_PAR_FEC_FEC0_ATA		(0x01)
+#define GPIO_PAR_FEC_FEC0_RMII_ULPI	(0x02)
+#define GPIO_PAR_FEC_FEC0_ULPI		(0x01)
 #define GPIO_PAR_FEC_FEC0_GPIO		(0x00)
 
 /* Bit definitions and macros for PAR_DMA */
diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h
index cd4d5dc9d9..1e060f7c31 100644
--- a/include/asm-mips/io.h
+++ b/include/asm-mips/io.h
@@ -71,7 +71,21 @@
  * instruction, so the lower 16 bits must be zero.  Should be true on
  * on any sane architecture; generic code does not use this assumption.
  */
-extern unsigned long mips_io_port_base;
+extern const unsigned long mips_io_port_base;
+
+/*
+ * Gcc will generate code to load the value of mips_io_port_base after each
+ * function call which may be fairly wasteful in some cases.  So we don't
+ * play quite by the book.  We tell gcc mips_io_port_base is a long variable
+ * which solves the code generation issue.  Now we need to violate the
+ * aliasing rules a little to make initialization possible and finally we
+ * will need the barrier() to fight side effects of the aliasing chat.
+ * This trickery will eventually collapse under gcc's optimizer.  Oh well.
+ */
+static inline void set_io_port_base(unsigned long base)
+{
+	* (unsigned long *) &mips_io_port_base = base;
+}
 
 /*
  * Thanks to James van Artsdalen for a better timing-fix than
diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index f580ccadee..13e2a2c079 100644
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -198,6 +198,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define PIXIS_VSPEED1		0x18	/* VELA VSpeed 1 */
 #define PIXIS_VCLKH		0x19	/* VELA VCLKH register */
 #define PIXIS_VCLKL		0x1A	/* VELA VCLKL register */
+#define CFG_PIXIS_VBOOT_MASK	0x40    /* Reset altbank mask*/
 
 
 /* define to use L1 as initial stack */
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index aa6dbc47ad..6f87240263 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -201,6 +201,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define PIXIS_VSPEED1		0x18	/* VELA VSpeed 1 */
 #define PIXIS_VCLKH		0x19	/* VELA VCLKH register */
 #define PIXIS_VCLKL		0x1A	/* VELA VCLKL register */
+#define CFG_PIXIS_VBOOT_MASK	0x40    /* Reset altbank mask*/
 
 #define CFG_MAX_FLASH_BANKS	2		/* number of banks */
 #define CFG_MAX_FLASH_SECT	128		/* sectors per device */
diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h
index 00c34d5d7b..52deab43f1 100644
--- a/include/configs/lwmon5.h
+++ b/include/configs/lwmon5.h
@@ -432,7 +432,7 @@
 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12				*/	\
 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO13				*/	\
 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14				*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO15				*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO15				*/	\
 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMCTxD(4)			*/	\
 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMCTxD(5)			*/	\
 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMCTxD(6)			*/	\
@@ -473,7 +473,7 @@
 {GPIO1_BASE, GPIO_IN,  GPIO_SEL , GPIO_OUT_0}, /* GPIO50  Unselect via TraceSelect Bit	*/	\
 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51  Unselect via TraceSelect Bit	*/	\
 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO53  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO53  Unselect via TraceSelect Bit	*/	\
 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO54  Unselect via TraceSelect Bit	*/	\
 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55  Unselect via TraceSelect Bit	*/	\
 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO56  Unselect via TraceSelect Bit	*/	\
diff --git a/include/configs/rsdproto.h b/include/configs/rsdproto.h
index 814082ccc6..40a05fa5e8 100644
--- a/include/configs/rsdproto.h
+++ b/include/configs/rsdproto.h
@@ -92,8 +92,8 @@
 
 /* enable I2C */
 #define CONFIG_HARD_I2C        	1	/* I2C with hardware support */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
+#define CFG_I2C_SPEED		50000	/* I2C speed and slave address */
+#define CFG_I2C_SLAVE		0x30
 
 
 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
diff --git a/include/miiphy.h b/include/miiphy.h
index 71716b04d4..5518a0a89c 100644
--- a/include/miiphy.h
+++ b/include/miiphy.h
@@ -26,56 +26,49 @@
 |
 |  Author:	Mark Wisner
 |
-|  Change Activity-
-|
-|  Date	       Description of Change					BY
-|  ---------   ---------------------					---
-|  04-May-99   Created							MKW
-|  07-Jul-99   Added full duplex support				MKW
-|  08-Sep-01   Tweaks							gvb
-|
 +----------------------------------------------------------------------------*/
 #ifndef _miiphy_h_
 #define _miiphy_h_
 
 #include <net.h>
 
-int  miiphy_read(char *devname, unsigned char addr, unsigned char reg,
-		unsigned short *value);
-int  miiphy_write(char *devname, unsigned char addr, unsigned char reg,
-		unsigned short value);
-int  miiphy_info(char *devname, unsigned char addr, unsigned int  *oui,
-		unsigned char *model, unsigned char *rev);
-int  miiphy_reset(char *devname, unsigned char addr);
-int  miiphy_speed(char *devname, unsigned char addr);
-int  miiphy_duplex(char *devname, unsigned char addr);
+int miiphy_read (char *devname, unsigned char addr, unsigned char reg,
+		 unsigned short *value);
+int miiphy_write (char *devname, unsigned char addr, unsigned char reg,
+		  unsigned short value);
+int miiphy_info (char *devname, unsigned char addr, unsigned int *oui,
+		 unsigned char *model, unsigned char *rev);
+int miiphy_reset (char *devname, unsigned char addr);
+int miiphy_speed (char *devname, unsigned char addr);
+int miiphy_duplex (char *devname, unsigned char addr);
+int miiphy_is_1000base_x (char *devname, unsigned char addr);
 #ifdef CFG_FAULT_ECHO_LINK_DOWN
-int  miiphy_link(char *devname, unsigned char addr);
+int miiphy_link (char *devname, unsigned char addr);
 #endif
 
-void miiphy_init(void);
+void miiphy_init (void);
 
-void miiphy_register(char *devname,
-	int (* read)(char *devname, unsigned char addr,
-		unsigned char reg, unsigned short *value),
-	int (* write)(char *devname, unsigned char addr,
-		unsigned char reg, unsigned short value));
+void miiphy_register (char *devname,
+		      int (*read) (char *devname, unsigned char addr,
+				   unsigned char reg, unsigned short *value),
+		      int (*write) (char *devname, unsigned char addr,
+				    unsigned char reg, unsigned short value));
 
-int miiphy_set_current_dev(char *devname);
-char *miiphy_get_current_dev(void);
+int miiphy_set_current_dev (char *devname);
+char *miiphy_get_current_dev (void);
 
-void miiphy_listdev(void);
+void miiphy_listdev (void);
 
 #define BB_MII_DEVNAME	"bbmii"
 
 int bb_miiphy_read (char *devname, unsigned char addr,
-		unsigned char reg, unsigned short *value);
+		    unsigned char reg, unsigned short *value);
 int bb_miiphy_write (char *devname, unsigned char addr,
-		unsigned char reg, unsigned short value);
+		     unsigned char reg, unsigned short value);
 
 /* phy seed setup */
 #define AUTO			99
-#define _1000BASET              1000
+#define _1000BASET		1000
 #define _100BASET		100
 #define _10BASET		10
 #define HALF			22
@@ -90,9 +83,10 @@ int bb_miiphy_write (char *devname, unsigned char addr,
 #define PHY_ANLPAR		0x05
 #define PHY_ANER		0x06
 #define PHY_ANNPTR		0x07
-#define PHY_ANLPNP              0x08
-#define PHY_1000BTCR            0x09
-#define PHY_1000BTSR            0x0A
+#define PHY_ANLPNP		0x08
+#define PHY_1000BTCR		0x09
+#define PHY_1000BTSR		0x0A
+#define PHY_EXSR		0x0F
 #define PHY_PHYSTS		0x10
 #define PHY_MIPSCR		0x11
 #define PHY_MIPGSR		0x12
@@ -115,10 +109,10 @@ int bb_miiphy_write (char *devname, unsigned char addr,
 #define PHY_BMCR_DPLX		0x0100
 #define PHY_BMCR_COL_TST	0x0080
 
-#define PHY_BMCR_SPEED_MASK     0x2040
-#define PHY_BMCR_1000_MBPS      0x0040
-#define PHY_BMCR_100_MBPS       0x2000
-#define PHY_BMCR_10_MBPS        0x0000
+#define PHY_BMCR_SPEED_MASK	0x2040
+#define PHY_BMCR_1000_MBPS	0x0040
+#define PHY_BMCR_100_MBPS	0x2000
+#define PHY_BMCR_10_MBPS	0x0000
 
 /* phy BMSR */
 #define PHY_BMSR_100T4		0x8000
@@ -126,6 +120,7 @@ int bb_miiphy_write (char *devname, unsigned char addr,
 #define PHY_BMSR_100TXH		0x2000
 #define PHY_BMSR_10TF		0x1000
 #define PHY_BMSR_10TH		0x0800
+#define PHY_BMSR_EXT_STAT	0x0100
 #define PHY_BMSR_PRE_SUP	0x0040
 #define PHY_BMSR_AUTN_COMP	0x0020
 #define PHY_BMSR_RF		0x0010
@@ -138,23 +133,42 @@ int bb_miiphy_write (char *devname, unsigned char addr,
 #define PHY_ANLPAR_NP		0x8000
 #define PHY_ANLPAR_ACK		0x4000
 #define PHY_ANLPAR_RF		0x2000
+#define PHY_ANLPAR_ASYMP	0x0800
+#define PHY_ANLPAR_PAUSE	0x0400
 #define PHY_ANLPAR_T4		0x0200
 #define PHY_ANLPAR_TXFD		0x0100
 #define PHY_ANLPAR_TX		0x0080
 #define PHY_ANLPAR_10FD		0x0040
 #define PHY_ANLPAR_10		0x0020
-#define PHY_ANLPAR_100		0x0380	    /* we can run at 100 */
-
-#define PHY_ANLPAR_PSB_MASK     0x001f
-#define PHY_ANLPAR_PSB_802_3    0x0001
-#define PHY_ANLPAR_PSB_802_9    0x0002
-
-/* PHY_1000BTSR */
-#define PHY_1000BTSR_MSCF       0x8000
-#define PHY_1000BTSR_MSCR       0x4000
-#define PHY_1000BTSR_LRS        0x2000
-#define PHY_1000BTSR_RRS        0x1000
-#define PHY_1000BTSR_1000FD     0x0800
-#define PHY_1000BTSR_1000HD     0x0400
+#define PHY_ANLPAR_100		0x0380	/* we can run at 100 */
+/* phy ANLPAR 1000BASE-X */
+#define PHY_X_ANLPAR_NP		0x8000
+#define PHY_X_ANLPAR_ACK	0x4000
+#define PHY_X_ANLPAR_RF_MASK	0x3000
+#define PHY_X_ANLPAR_PAUSE_MASK	0x0180
+#define PHY_X_ANLPAR_HD		0x0040
+#define PHY_X_ANLPAR_FD		0x0020
+
+#define PHY_ANLPAR_PSB_MASK	0x001f
+#define PHY_ANLPAR_PSB_802_3	0x0001
+#define PHY_ANLPAR_PSB_802_9	0x0002
+
+/* phy 1000BTCR */
+#define PHY_1000BTCR_1000FD	0x0200
+#define PHY_1000BTCR_1000HD	0x0100
+
+/* phy 1000BTSR */
+#define PHY_1000BTSR_MSCF	0x8000
+#define PHY_1000BTSR_MSCR	0x4000
+#define PHY_1000BTSR_LRS	0x2000
+#define PHY_1000BTSR_RRS	0x1000
+#define PHY_1000BTSR_1000FD	0x0800
+#define PHY_1000BTSR_1000HD	0x0400
+
+/* phy EXSR */
+#define PHY_EXSR_1000XF		0x8000
+#define PHY_EXSR_1000XH		0x4000
+#define PHY_EXSR_1000TF		0x2000
+#define PHY_EXSR_1000TH		0x1000
 
 #endif