ColdFire: Add DSPI support for MCF5227x and MCF5445x

Remove individual CPU specific DSPI driver.
Add required feature for the common DSPI driver in cpu_init and
in platform configuration file.

Signed-off-by: TsiChung Liew <tsicliew@gmail.com>

4 files changed, 142 insertions, 173 deletions

diff --git a/include/asm-m68k/coldfire/dspi.h b/include/asm-m68k/coldfire/dspi.h
index 4b7d61e0fe..02d1409610 100644
--- a/include/asm-m68k/coldfire/dspi.h
+++ b/include/asm-m68k/coldfire/dspi.h
@@ -26,140 +26,133 @@
 #ifndef __DSPI_H__
 #define __DSPI_H__
 
-/*********************************************************************
-* DMA Serial Peripheral Interface (DSPI)
-*********************************************************************/
-
+/* DMA Serial Peripheral Interface (DSPI) */
 typedef struct dspi {
-	u32 dmcr;
-	u8 resv0[0x4];
-	u32 dtcr;
-	u32 dctar0;
-	u32 dctar1;
-	u32 dctar2;
-	u32 dctar3;
-	u32 dctar4;
-	u32 dctar5;
-	u32 dctar6;
-	u32 dctar7;
-	u32 dsr;
-	u32 dirsr;
-	u32 dtfr;
-	u32 drfr;
+	u32 mcr;	/* 0x00 */
+	u32 resv0;	/* 0x04 */
+	u32 tcr;	/* 0x08 */
+	u32 ctar[8];	/* 0x0C - 0x28 */
+	u32 sr;		/* 0x2C */
+	u32 irsr;	/* 0x30 */
+	u32 tfr;	/* 0x34 - PUSHR */
+	u16 resv1;	/* 0x38 */
+	u16 rfr;	/* 0x3A - POPR */
 #ifdef CONFIG_MCF547x_8x
-	u32 dtfdr[4];
-	u8 resv1[0x30];
-	u32 drfdr[4];
+	u32 tfdr[4];	/* 0x3C */
+	u8 resv2[0x30];	/* 0x40 */
+	u32 rfdr[4];	/* 0x7C */
 #else
-	u32 dtfdr[16];
-	u32 drfdr[16];
+	u32 tfdr[16];	/* 0x3C */
+	u32 rfdr[16];	/* 0x7C */
 #endif
 } dspi_t;
 
-/* Bit definitions and macros for DMCR */
-#define DSPI_DMCR_HALT			(0x00000001)
-#define DSPI_DMCR_SMPL_PT(x)		(((x)&0x00000003)<<8)
-#define DSPI_DMCR_CRXF			(0x00000400)
-#define DSPI_DMCR_CTXF			(0x00000800)
-#define DSPI_DMCR_DRXF			(0x00001000)
-#define DSPI_DMCR_DTXF			(0x00002000)
-#define DSPI_DMCR_MDIS			(0x00004000)
-#define DSPI_DMCR_CSIS0			(0x00010000)
-#define DSPI_DMCR_CSIS1			(0x00020000)
-#define DSPI_DMCR_CSIS2			(0x00040000)
-#define DSPI_DMCR_CSIS3			(0x00080000)
-#define DSPI_DMCR_CSIS4			(0x00100000)
-#define DSPI_DMCR_CSIS5			(0x00200000)
-#define DSPI_DMCR_CSIS6			(0x00400000)
-#define DSPI_DMCR_CSIS7			(0x00800000)
-#define DSPI_DMCR_ROOE			(0x01000000)
-#define DSPI_DMCR_PCSSE			(0x02000000)
-#define DSPI_DMCR_MTFE			(0x04000000)
-#define DSPI_DMCR_FRZ			(0x08000000)
-#define DSPI_DMCR_DCONF(x)		(((x)&0x00000003)<<28)
-#define DSPI_DMCR_CSCK			(0x40000000)
-#define DSPI_DMCR_MSTR			(0x80000000)
+/* Module configuration */
+#define DSPI_MCR_MSTR			(0x80000000)
+#define DSPI_MCR_CSCK			(0x40000000)
+#define DSPI_MCR_DCONF(x)		(((x)&0x03)<<28)
+#define DSPI_MCR_FRZ			(0x08000000)
+#define DSPI_MCR_MTFE			(0x04000000)
+#define DSPI_MCR_PCSSE			(0x02000000)
+#define DSPI_MCR_ROOE			(0x01000000)
+#define DSPI_MCR_CSIS7			(0x00800000)
+#define DSPI_MCR_CSIS6			(0x00400000)
+#define DSPI_MCR_CSIS5			(0x00200000)
+#define DSPI_MCR_CSIS4			(0x00100000)
+#define DSPI_MCR_CSIS3			(0x00080000)
+#define DSPI_MCR_CSIS2			(0x00040000)
+#define DSPI_MCR_CSIS1			(0x00020000)
+#define DSPI_MCR_CSIS0			(0x00010000)
+#define DSPI_MCR_MDIS			(0x00004000)
+#define DSPI_MCR_DTXF			(0x00002000)
+#define DSPI_MCR_DRXF			(0x00001000)
+#define DSPI_MCR_CTXF			(0x00000800)
+#define DSPI_MCR_CRXF			(0x00000400)
+#define DSPI_MCR_SMPL_PT(x)		(((x)&0x03)<<8)
+#define DSPI_MCR_HALT			(0x00000001)
+
+/* Transfer count */
+#define DSPI_TCR_SPI_TCNT(x)		(((x)&0x0000FFFF)<<16)
 
-/* Bit definitions and macros for DTCR */
-#define DSPI_DTCR_SPI_TCNT(x)		(((x)&0x0000FFFF)<<16)
+/* Clock and transfer attributes */
+#define DSPI_CTAR_DBR			(0x80000000)
+#define DSPI_CTAR_TRSZ(x)		(((x)&0x0F)<<27)
+#define DSPI_CTAR_CPOL			(0x04000000)
+#define DSPI_CTAR_CPHA			(0x02000000)
+#define DSPI_CTAR_LSBFE			(0x01000000)
+#define DSPI_CTAR_PCSSCK(x)		(((x)&0x03)<<22)
+#define DSPI_CTAR_PCSSCK_7CLK		(0x00A00000)
+#define DSPI_CTAR_PCSSCK_5CLK		(0x00800000)
+#define DSPI_CTAR_PCSSCK_3CLK		(0x00400000)
+#define DSPI_CTAR_PCSSCK_1CLK		(0x00000000)
+#define DSPI_CTAR_PASC(x)		(((x)&0x03)<<20)
+#define DSPI_CTAR_PASC_7CLK		(0x00300000)
+#define DSPI_CTAR_PASC_5CLK		(0x00200000)
+#define DSPI_CTAR_PASC_3CLK		(0x00100000)
+#define DSPI_CTAR_PASC_1CLK		(0x00000000)
+#define DSPI_CTAR_PDT(x)		(((x)&0x03)<<18)
+#define DSPI_CTAR_PDT_7CLK		(0x000A0000)
+#define DSPI_CTAR_PDT_5CLK		(0x00080000)
+#define DSPI_CTAR_PDT_3CLK		(0x00040000)
+#define DSPI_CTAR_PDT_1CLK		(0x00000000)
+#define DSPI_CTAR_PBR(x)		(((x)&0x03)<<16)
+#define DSPI_CTAR_PBR_7CLK		(0x00030000)
+#define DSPI_CTAR_PBR_5CLK		(0x00020000)
+#define DSPI_CTAR_PBR_3CLK		(0x00010000)
+#define DSPI_CTAR_PBR_1CLK		(0x00000000)
+#define DSPI_CTAR_CSSCK(x)		(((x)&0x0F)<<12)
+#define DSPI_CTAR_ASC(x)		(((x)&0x0F)<<8)
+#define DSPI_CTAR_DT(x)			(((x)&0x0F)<<4)
+#define DSPI_CTAR_BR(x)			(((x)&0x0F))
 
-/* Bit definitions and macros for DCTAR group */
-#define DSPI_DCTAR_BR(x)		(((x)&0x0000000F))
-#define DSPI_DCTAR_DT(x)		(((x)&0x0000000F)<<4)
-#define DSPI_DCTAR_ASC(x)		(((x)&0x0000000F)<<8)
-#define DSPI_DCTAR_CSSCK(x)		(((x)&0x0000000F)<<12)
-#define DSPI_DCTAR_PBR(x)		(((x)&0x00000003)<<16)
-#define DSPI_DCTAR_PDT(x)		(((x)&0x00000003)<<18)
-#define DSPI_DCTAR_PASC(x)		(((x)&0x00000003)<<20)
-#define DSPI_DCTAR_PCSSCK(x)		(((x)&0x00000003)<<22)
-#define DSPI_DCTAR_LSBFE		(0x01000000)
-#define DSPI_DCTAR_CPHA			(0x02000000)
-#define DSPI_DCTAR_CPOL			(0x04000000)
-#define DSPI_DCTAR_TRSZ(x)		(((x)&0x0000000F)<<27)
-#define DSPI_DCTAR_DBR			(0x80000000)
-#define DSPI_DCTAR_PCSSCK_1CLK		(0x00000000)
-#define DSPI_DCTAR_PCSSCK_3CLK		(0x00400000)
-#define DSPI_DCTAR_PCSSCK_5CLK		(0x00800000)
-#define DSPI_DCTAR_PCSSCK_7CLK		(0x00A00000)
-#define DSPI_DCTAR_PASC_1CLK		(0x00000000)
-#define DSPI_DCTAR_PASC_3CLK		(0x00100000)
-#define DSPI_DCTAR_PASC_5CLK		(0x00200000)
-#define DSPI_DCTAR_PASC_7CLK		(0x00300000)
-#define DSPI_DCTAR_PDT_1CLK		(0x00000000)
-#define DSPI_DCTAR_PDT_3CLK		(0x00040000)
-#define DSPI_DCTAR_PDT_5CLK		(0x00080000)
-#define DSPI_DCTAR_PDT_7CLK		(0x000A0000)
-#define DSPI_DCTAR_PBR_1CLK		(0x00000000)
-#define DSPI_DCTAR_PBR_3CLK		(0x00010000)
-#define DSPI_DCTAR_PBR_5CLK		(0x00020000)
-#define DSPI_DCTAR_PBR_7CLK		(0x00030000)
+/* Status */
+#define DSPI_SR_TCF			(0x80000000)
+#define DSPI_SR_TXRXS			(0x40000000)
+#define DSPI_SR_EOQF			(0x10000000)
+#define DSPI_SR_TFUF			(0x08000000)
+#define DSPI_SR_TFFF			(0x02000000)
+#define DSPI_SR_RFOF			(0x00080000)
+#define DSPI_SR_RFDF			(0x00020000)
+#define DSPI_SR_TXCTR(x)		(((x)&0x0F)<<12)
+#define DSPI_SR_TXPTR(x)		(((x)&0x0F)<<8)
+#define DSPI_SR_RXCTR(x)		(((x)&0x0F)<<4)
+#define DSPI_SR_RXPTR(x)		(((x)&0x0F))
 
-/* Bit definitions and macros for DSR */
-#define DSPI_DSR_RXPTR(x)		(((x)&0x0000000F))
-#define DSPI_DSR_RXCTR(x)		(((x)&0x0000000F)<<4)
-#define DSPI_DSR_TXPTR(x)		(((x)&0x0000000F)<<8)
-#define DSPI_DSR_TXCTR(x)		(((x)&0x0000000F)<<12)
-#define DSPI_DSR_RFDF			(0x00020000)
-#define DSPI_DSR_RFOF			(0x00080000)
-#define DSPI_DSR_TFFF			(0x02000000)
-#define DSPI_DSR_TFUF			(0x08000000)
-#define DSPI_DSR_EOQF			(0x10000000)
-#define DSPI_DSR_TXRXS			(0x40000000)
-#define DSPI_DSR_TCF			(0x80000000)
+/* DMA/interrupt request selct and enable */
+#define DSPI_IRSR_TCFE			(0x80000000)
+#define DSPI_IRSR_EOQFE			(0x10000000)
+#define DSPI_IRSR_TFUFE			(0x08000000)
+#define DSPI_IRSR_TFFFE			(0x02000000)
+#define DSPI_IRSR_TFFFS			(0x01000000)
+#define DSPI_IRSR_RFOFE			(0x00080000)
+#define DSPI_IRSR_RFDFE			(0x00020000)
+#define DSPI_IRSR_RFDFS			(0x00010000)
 
-/* Bit definitions and macros for DIRSR */
-#define DSPI_DIRSR_RFDFS		(0x00010000)
-#define DSPI_DIRSR_RFDFE		(0x00020000)
-#define DSPI_DIRSR_RFOFE		(0x00080000)
-#define DSPI_DIRSR_TFFFS		(0x01000000)
-#define DSPI_DIRSR_TFFFE		(0x02000000)
-#define DSPI_DIRSR_TFUFE		(0x08000000)
-#define DSPI_DIRSR_EOQFE		(0x10000000)
-#define DSPI_DIRSR_TCFE			(0x80000000)
+/* Transfer control - 32-bit access */
+#define DSPI_TFR_CONT			(0x80000000)
+#define DSPI_TFR_CTAS(x)		(((x)&0x07)<<12)
+#define DSPI_TFR_EOQ			(0x08000000)
+#define DSPI_TFR_CTCNT			(0x04000000)
+#define DSPI_TFR_CS7			(0x00800000)
+#define DSPI_TFR_CS6			(0x00400000)
+#define DSPI_TFR_CS5			(0x00200000)
+#define DSPI_TFR_CS4			(0x00100000)
+#define DSPI_TFR_CS3			(0x00080000)
+#define DSPI_TFR_CS2			(0x00040000)
+#define DSPI_TFR_CS1			(0x00020000)
+#define DSPI_TFR_CS0			(0x00010000)
 
-/* Bit definitions and macros for DTFR */
-#define DSPI_DTFR_TXDATA(x)		(((x)&0x0000FFFF))
-#define DSPI_DTFR_CS0			(0x00010000)
-#define DSPI_DTFR_CS2			(0x00040000)
-#define DSPI_DTFR_CS3			(0x00080000)
-#define DSPI_DTFR_CS5			(0x00200000)
-#define DSPI_DTFR_CTCNT			(0x04000000)
-#define DSPI_DTFR_EOQ			(0x08000000)
-#define DSPI_DTFR_CTAS(x)		(((x)&0x00000007)<<28)
-#define DSPI_DTFR_CONT			(0x80000000)
+/* Transfer Fifo */
+#define DSPI_TFR_TXDATA(x)		(((x)&0xFFFF))
 
 /* Bit definitions and macros for DRFR */
-#define DSPI_DRFR_RXDATA(x)		(((x)&0x0000FFFF))
+#define DSPI_RFR_RXDATA(x)		(((x)&0xFFFF))
 
 /* Bit definitions and macros for DTFDR group */
-#define DSPI_DTFDR_TXDATA(x)		(((x)&0x0000FFFF))
-#define DSPI_DTFDR_TXCMD(x)		(((x)&0x0000FFFF)<<16)
+#define DSPI_TFDR_TXDATA(x)		(((x)&0x0000FFFF))
+#define DSPI_TFDR_TXCMD(x)		(((x)&0x0000FFFF)<<16)
 
 /* Bit definitions and macros for DRFDR group */
-#define DSPI_DRFDR_RXDATA(x)		(((x)&0x0000FFFF))
-
-void dspi_init(void);
-void dspi_tx(int chipsel, u8 attrib, u16 data);
-u16 dspi_rx(void);
+#define DSPI_RFDR_RXDATA(x)		(((x)&0x0000FFFF))
 
 #endif				/* __DSPI_H__ */
diff --git a/include/configs/M52277EVB.h b/include/configs/M52277EVB.h
index 77a38ecd02..e7db0cc108 100644
--- a/include/configs/M52277EVB.h
+++ b/include/configs/M52277EVB.h
@@ -154,26 +154,22 @@
 #define CONFIG_SYS_IMMR			CONFIG_SYS_MBAR
 
 /* DSPI and Serial Flash */
+#define CONFIG_CF_SPI
 #define CONFIG_CF_DSPI
 #define CONFIG_HARD_SPI
-#define CONFIG_SYS_SER_FLASH_BASE	0x01000000
 #define CONFIG_SYS_SBFHDR_SIZE		0x7
 #ifdef CONFIG_CMD_SPI
 #	define CONFIG_SYS_DSPI_CS2
 #	define CONFIG_SPI_FLASH
 #	define CONFIG_SPI_FLASH_STMICRO
 
-#	define CONFIG_SYS_DSPI_DCTAR0	(DSPI_DCTAR_TRSZ(7) | \
-					 DSPI_DCTAR_CPOL | \
-					 DSPI_DCTAR_CPHA | \
-					 DSPI_DCTAR_PCSSCK_1CLK | \
-					 DSPI_DCTAR_PASC(0) | \
-					 DSPI_DCTAR_PDT(0) | \
-					 DSPI_DCTAR_CSSCK(0) | \
-					 DSPI_DCTAR_ASC(0) | \
-					 DSPI_DCTAR_PBR(0) | \
-					 DSPI_DCTAR_DT(1) | \
-					 DSPI_DCTAR_BR(1))
+#	define CONFIG_SYS_DSPI_CTAR0	(DSPI_CTAR_TRSZ(7) | \
+					 DSPI_CTAR_PCSSCK_1CLK | \
+					 DSPI_CTAR_PASC(0) | \
+					 DSPI_CTAR_PDT(0) | \
+					 DSPI_CTAR_CSSCK(0) | \
+					 DSPI_CTAR_ASC(0) | \
+					 DSPI_CTAR_DT(1))
 #endif
 
 /* Input, PCI, Flexbus, and VCO */
@@ -265,9 +261,7 @@
  * FLASH organization
  */
 #ifdef CONFIG_SYS_STMICRO_BOOT
-#	define CONFIG_SYS_FLASH_BASE	CONFIG_SYS_SER_FLASH_BASE
-#	define CONFIG_SYS_FLASH0_BASE	CONFIG_SYS_SER_FLASH_BASE
-#	define CONFIG_SYS_FLASH1_BASE	CONFIG_SYS_CS0_BASE
+#	define CONFIG_SYS_FLASH_BASE	CONFIG_SYS_CS0_BASE
 #	define CONFIG_ENV_OFFSET	0x30000
 #	define CONFIG_ENV_SIZE		0x1000
 #	define CONFIG_ENV_SECT_SIZE	0x10000
diff --git a/include/configs/M54451EVB.h b/include/configs/M54451EVB.h
index cc57da816b..69bb26b8ae 100644
--- a/include/configs/M54451EVB.h
+++ b/include/configs/M54451EVB.h
@@ -167,26 +167,24 @@
 #define CONFIG_SYS_IMMR			CONFIG_SYS_MBAR
 
 /* DSPI and Serial Flash */
+#define CONFIG_CF_SPI
 #define CONFIG_CF_DSPI
 #define CONFIG_SERIAL_FLASH
 #define CONFIG_HARD_SPI
-#define CONFIG_SYS_SER_FLASH_BASE	0x01000000
 #define CONFIG_SYS_SBFHDR_SIZE		0x7
 #ifdef CONFIG_CMD_SPI
 #	define CONFIG_SPI_FLASH
 #	define CONFIG_SPI_FLASH_STMICRO
 
-#	define CONFIG_SYS_DSPI_DCTAR0	(DSPI_DCTAR_TRSZ(7) | \
-					 DSPI_DCTAR_CPOL | \
-					 DSPI_DCTAR_CPHA | \
-					 DSPI_DCTAR_PCSSCK_1CLK | \
-					 DSPI_DCTAR_PASC(0) | \
-					 DSPI_DCTAR_PDT(0) | \
-					 DSPI_DCTAR_CSSCK(0) | \
-					 DSPI_DCTAR_ASC(0) | \
-					 DSPI_DCTAR_PBR(0) | \
-					 DSPI_DCTAR_DT(1) | \
-					 DSPI_DCTAR_BR(1))
+#	define CONFIG_SYS_DSPI_CTAR0	(DSPI_CTAR_TRSZ(7) | \
+					 DSPI_CTAR_PCSSCK_1CLK | \
+					 DSPI_CTAR_PASC(0) | \
+					 DSPI_CTAR_PDT(0) | \
+					 DSPI_CTAR_CSSCK(0) | \
+					 DSPI_CTAR_ASC(0) | \
+					 DSPI_CTAR_DT(1))
+#	define CONFIG_SYS_DSPI_CTAR1	(CONFIG_SYS_DSPI_CTAR0)
+#	define CONFIG_SYS_DSPI_CTAR2	(CONFIG_SYS_DSPI_CTAR0)
 #endif
 
 /* Input, PCI, Flexbus, and VCO */
@@ -281,18 +279,8 @@
 #undef CONFIG_ENV_OVERWRITE
 #undef CONFIG_ENV_IS_EMBEDDED
 
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#ifdef CONFIG_SYS_STMICRO_BOOT
-#	define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_SER_FLASH_BASE
-#	define CONFIG_SYS_FLASH0_BASE		CONFIG_SYS_SER_FLASH_BASE
-#	define CONFIG_SYS_FLASH1_BASE		CONFIG_SYS_CS0_BASE
-#else
-#	define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
-#	define CONFIG_SYS_FLASH0_BASE		CONFIG_SYS_CS0_BASE
-#	define CONFIG_SYS_FLASH1_BASE		CONFIG_SYS_SER_FLASH_BASE
-#endif
+/* FLASH organization */
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
 
 #define CONFIG_SYS_FLASH_CFI
 #ifdef CONFIG_SYS_FLASH_CFI
diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h
index 4e33171986..14d98d69c8 100644
--- a/include/configs/M54455EVB.h
+++ b/include/configs/M54455EVB.h
@@ -200,25 +200,21 @@
 #define CONFIG_SYS_IMMR		CONFIG_SYS_MBAR
 
 /* DSPI and Serial Flash */
+#define CONFIG_CF_SPI
 #define CONFIG_CF_DSPI
 #define CONFIG_HARD_SPI
-#define CONFIG_SYS_SER_FLASH_BASE	0x01000000
 #define CONFIG_SYS_SBFHDR_SIZE		0x13
 #ifdef CONFIG_CMD_SPI
 #	define CONFIG_SPI_FLASH
 #	define CONFIG_SPI_FLASH_STMICRO
 
-#	define CONFIG_SYS_DSPI_DCTAR0		(DSPI_DCTAR_TRSZ(7) | \
-					 DSPI_DCTAR_CPOL | \
-					 DSPI_DCTAR_CPHA | \
-					 DSPI_DCTAR_PCSSCK_1CLK | \
-					 DSPI_DCTAR_PASC(0) | \
-					 DSPI_DCTAR_PDT(0) | \
-					 DSPI_DCTAR_CSSCK(0) | \
-					 DSPI_DCTAR_ASC(0) | \
-					 DSPI_DCTAR_PBR(0) | \
-					 DSPI_DCTAR_DT(1) | \
-					 DSPI_DCTAR_BR(1))
+#	define CONFIG_SYS_DSPI_CTAR0		(DSPI_CTAR_TRSZ(7) | \
+					 DSPI_CTAR_PCSSCK_1CLK | \
+					 DSPI_CTAR_PASC(0) | \
+					 DSPI_CTAR_PDT(0) | \
+					 DSPI_CTAR_CSSCK(0) | \
+					 DSPI_CTAR_ASC(0) | \
+					 DSPI_CTAR_DT(1))
 #endif
 
 /* PCI */
@@ -342,10 +338,8 @@
  * FLASH organization
  */
 #ifdef CONFIG_SYS_STMICRO_BOOT
-#	define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_SER_FLASH_BASE
-#	define CONFIG_SYS_FLASH0_BASE		CONFIG_SYS_SER_FLASH_BASE
-#	define CONFIG_SYS_FLASH1_BASE		CONFIG_SYS_CS0_BASE
-#	define CONFIG_SYS_FLASH2_BASE		CONFIG_SYS_CS1_BASE
+#	define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
+#	define CONFIG_SYS_FLASH0_BASE		CONFIG_SYS_CS1_BASE
 #	define CONFIG_ENV_OFFSET		0x30000
 #	define CONFIG_ENV_SIZE		0x2000
 #	define CONFIG_ENV_SECT_SIZE	0x10000