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authorTom Rini <trini@konsulko.com>2015-08-17 17:19:40 -0400
committerTom Rini <trini@konsulko.com>2015-08-17 17:19:40 -0400
commitecd37e8598128e2b9b21f7857f81852bd779b728 (patch)
treecf50ca35106c87553b00d982c80ec1bc688d1391 /include
parent2212e69bc09ac42593794b030d64415293e141ec (diff)
parentce2cb1d3ed92e91b24db516802be3688f7c28e26 (diff)
downloadtalos-obmc-uboot-ecd37e8598128e2b9b21f7857f81852bd779b728.tar.gz
talos-obmc-uboot-ecd37e8598128e2b9b21f7857f81852bd779b728.zip
Merge git://git.denx.de/u-boot-marvell
Diffstat (limited to 'include')
-rw-r--r--include/configs/db-88f6820-gp.h15
-rw-r--r--include/configs/db-mv784mp-gp.h24
-rw-r--r--include/configs/maxbcm.h7
3 files changed, 43 insertions, 3 deletions
diff --git a/include/configs/db-88f6820-gp.h b/include/configs/db-88f6820-gp.h
index 739c2bf3d5..1dd4182136 100644
--- a/include/configs/db-88f6820-gp.h
+++ b/include/configs/db-88f6820-gp.h
@@ -20,7 +20,12 @@
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_DISPLAY_BOARDINFO_LATE
-#define CONFIG_SYS_TEXT_BASE 0x04000000
+/*
+ * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
+ * for DDR ECC byte filling in the SPL before loading the main
+ * U-Boot into it.
+ */
+#define CONFIG_SYS_TEXT_BASE 0x00800000
#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
/*
@@ -36,6 +41,7 @@
#define CONFIG_CMD_FS_GENERIC
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MMC
+#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
#define CONFIG_CMD_SCSI
#define CONFIG_CMD_SF
@@ -101,6 +107,13 @@
#define CONFIG_SYS_NETA_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
+/* PCIe support */
+#define CONFIG_PCI
+#define CONFIG_PCI_MVEBU
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_E1000 /* enable Intel E1000 support for testing */
+
#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */
#define CONFIG_SYS_ALT_MEMTEST
diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h
index 41e6fdcb52..eec2ba933f 100644
--- a/include/configs/db-mv784mp-gp.h
+++ b/include/configs/db-mv784mp-gp.h
@@ -17,7 +17,12 @@
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_DISPLAY_BOARDINFO_LATE
-#define CONFIG_SYS_TEXT_BASE 0x04000000
+/*
+ * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
+ * for DDR ECC byte filling in the SPL before loading the main
+ * U-Boot into it.
+ */
+#define CONFIG_SYS_TEXT_BASE 0x00800000
#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
/*
@@ -28,11 +33,13 @@
#define CONFIG_CMD_ENV
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IDE
+#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
#define CONFIG_CMD_SF
#define CONFIG_CMD_SPI
#define CONFIG_CMD_TFTPPUT
#define CONFIG_CMD_TIME
+#define CONFIG_CMD_USB
/* I2C */
#define CONFIG_SYS_I2C
@@ -41,6 +48,13 @@
#define CONFIG_SYS_I2C_SLAVE 0x0
#define CONFIG_SYS_I2C_SPEED 100000
+/* USB/EHCI configuration */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_EHCI_MARVELL
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
+
/* SPI NOR flash default params, used by sf commands */
#define CONFIG_SF_DEFAULT_SPEED 1000000
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
@@ -89,6 +103,13 @@
#define CONFIG_DOS_PARTITION
#endif /* CONFIG_CMD_IDE */
+/* PCIe support */
+#define CONFIG_PCI
+#define CONFIG_PCI_MVEBU
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_E1000 /* enable Intel E1000 support for testing */
+
/*
* mv-common.h should be defined after CMD configs since it used them
* to enable certain macros
@@ -136,6 +157,7 @@
#define CONFIG_SPL_SPI_BUS 0
#define CONFIG_SPL_SPI_CS 0
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
+#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
#define CONFIG_SYS_MVEBU_DDR_AXP
diff --git a/include/configs/maxbcm.h b/include/configs/maxbcm.h
index 0fb117f9d3..3530a26213 100644
--- a/include/configs/maxbcm.h
+++ b/include/configs/maxbcm.h
@@ -15,7 +15,12 @@
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_DISPLAY_BOARDINFO_LATE
-#define CONFIG_SYS_TEXT_BASE 0x04000000
+/*
+ * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
+ * for DDR ECC byte filling in the SPL before loading the main
+ * U-Boot into it.
+ */
+#define CONFIG_SYS_TEXT_BASE 0x00800000
#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
/*
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