Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx

* 'master' of git://git.denx.de/u-boot-ppc4xx:
  board/mpl/pati: use the CFI driver for the PATI board
  board/mpl/mip405: use the CFI driver for the MIP405/MIP405T board
  board/mpl/pip405: use the CFI driver for the PIP405 board
  board/mpl/common: remove the old legacy flash
  ppc4xx: Setup HICB on Io64

4 files changed, 36 insertions, 13 deletions

diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h
index 247cd2ff6e..9961fb55ca 100644
--- a/include/configs/MIP405.h
+++ b/include/configs/MIP405.h
@@ -239,11 +239,17 @@
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_UPDATE_FLASH_SIZE
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_FLASH_EMPTY_INFO
 
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+
+#define CONFIG_FLASH_SHOW_PROGRESS	45
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	256
 
 /*
  * JFFS2 partitions
@@ -291,6 +297,7 @@
 #define FLASH_SIZE_PRELIM	 3  /* maximal flash FLASH size bank #0	*/
 
 #define CONFIG_BOARD_EARLY_INIT_F 1
+#define CONFIG_BOARD_EARLY_INIT_R
 
 /* Peripheral Bus Mapping */
 #define PER_PLD_ADDR		0xF4000000 /* smallest window is 1MByte 0x10 0000*/
diff --git a/include/configs/PATI.h b/include/configs/PATI.h
index da2d602506..bf39d0040e 100644
--- a/include/configs/PATI.h
+++ b/include/configs/PATI.h
@@ -168,11 +168,16 @@
  *
  */
 
-#define CONFIG_SYS_MAX_FLASH_BANKS		1		/* Max number of memory banks		*/
-#define CONFIG_SYS_MAX_FLASH_SECT		128		/* Max number of sectors on one chip	*/
-#define CONFIG_SYS_FLASH_ERASE_TOUT	180000		/* Timeout for Flash Erase (in ms)	*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT	600		/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_FLASH_EMPTY_INFO
 
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+
+#define CONFIG_FLASH_SHOW_PROGRESS	45
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	128
 
 #define	CONFIG_ENV_IS_IN_EEPROM
 #ifdef	CONFIG_ENV_IS_IN_EEPROM
diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h
index 07415f4b57..242aa314a1 100644
--- a/include/configs/PIP405.h
+++ b/include/configs/PIP405.h
@@ -113,6 +113,8 @@
 #define SPD_EEPROM_ADDRESS      0x50
 
 #define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_EARLY_INIT_R
+
 /**************************************************************
  * Environment definitions
  **************************************************************/
@@ -230,11 +232,17 @@
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_UPDATE_FLASH_SIZE
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+
+#define CONFIG_FLASH_SHOW_PROGRESS	45
 
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	256
 
 /*
  * Init Memory Controller:
diff --git a/include/gdsys_fpga.h b/include/gdsys_fpga.h
index e7a072bbe8..949864c0f2 100644
--- a/include/gdsys_fpga.h
+++ b/include/gdsys_fpga.h
@@ -82,7 +82,10 @@ typedef struct ihs_fpga {
 	u16 reserved_1[502];	/* 0x0014 */
 	u16 ch0_status_int;	/* 0x0400 */
 	u16 ch0_config_int;	/* 0x0402 */
-	u16 reserved_2[7677];	/* 0x0404 */
+	u16 reserved_2[126];	/* 0x0404 */
+	u16 ch0_hicb_status_int;/* 0x0500 */
+	u16 ch0_hicb_config_int;/* 0x0502 */
+	u16 reserved_3[7549];	/* 0x0504 */
 	u16 reflection_high;	/* 0x3ffe */
 } ihs_fpga_t;
 #endif