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authorwdenk <wdenk>2004-01-02 16:05:07 +0000
committerwdenk <wdenk>2004-01-02 16:05:07 +0000
commitb6e4c4033c4f889c452c511d38c77808c67f9cf7 (patch)
tree73a39833805f4cf47588dd1616a1b479ab58a418 /include
parent63f3491242df8e6bd1b5df7296f28959989e2eaf (diff)
downloadtalos-obmc-uboot-b6e4c4033c4f889c452c511d38c77808c67f9cf7.tar.gz
talos-obmc-uboot-b6e4c4033c4f889c452c511d38c77808c67f9cf7.zip
* Patch by Denis Peter, 8 Dec 2003
- add support for the PATI board (MPC555) - add SPI support for the MPC5xx * Patch by Anders Larsen, 08 Dec 2003: add configuration options CONFIG_SERIAL_TAG and CONFIG_REVISION_TAG to pass ATAG_SERIAL and ATAG_REVISION, resp., to the ARM target; cleanup some redundand #defines
Diffstat (limited to 'include')
-rw-r--r--include/asm-arm/u-boot-arm.h2
-rw-r--r--include/common.h1
-rw-r--r--include/configs/PATI.h285
-rw-r--r--include/mpc5xx.h14
4 files changed, 299 insertions, 3 deletions
diff --git a/include/asm-arm/u-boot-arm.h b/include/asm-arm/u-boot-arm.h
index 4c92b1f361..d5dbd6d1ba 100644
--- a/include/asm-arm/u-boot-arm.h
+++ b/include/asm-arm/u-boot-arm.h
@@ -43,6 +43,8 @@ int cleanup_before_linux(void);
/* board/.../... */
int board_init(void);
int dram_init (void);
+void setup_serial_tag (struct tag **params);
+void setup_revision_tag (struct tag **params);
/* ------------------------------------------------------------ */
/* Here is a list of some prototypes which are incompatible to */
diff --git a/include/common.h b/include/common.h
index 73a5a2e880..6b92548243 100644
--- a/include/common.h
+++ b/include/common.h
@@ -185,6 +185,7 @@ void inline setenv (char *, char *);
void setenv (char *, char *);
#endif /* CONFIG_PPC */
#ifdef CONFIG_ARM
+# include <asm/setup.h>
# include <asm/u-boot-arm.h> /* ARM version to be fixed! */
#endif /* CONFIG_ARM */
#ifdef CONFIG_I386 /* x86 version to be fixed! */
diff --git a/include/configs/PATI.h b/include/configs/PATI.h
new file mode 100644
index 0000000000..42c78d462b
--- /dev/null
+++ b/include/configs/PATI.h
@@ -0,0 +1,285 @@
+/*
+ * (C) Copyright 2003
+ * Denis Peter d.peter@mpl.ch
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation,
+ */
+
+/*
+ * File: PATI.h
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+
+#define CONFIG_MPC555 1 /* This is an MPC555 CPU */
+#define CONFIG_PATI 1 /* ...On a PATI board */
+/* Serial Console Configuration */
+#define CONFIG_5xx_CONS_SCI1
+#undef CONFIG_5xx_CONS_SCI2
+
+#define CONFIG_BAUDRATE 9600
+
+#define CONFIG_COMMANDS (CFG_CMD_MEMORY | CFG_CMD_LOADB | CFG_CMD_REGINFO | \
+ CFG_CMD_FLASH | CFG_CMD_LOADS | CFG_CMD_ENV | CFG_CMD_REGINFO | \
+ CFG_CMD_BDI | CFG_CMD_CONSOLE | CFG_CMD_RUN | CFG_CMD_BSP | \
+ CFG_CMD_IMI | CFG_CMD_EEPROM | CFG_CMD_IRQ | CFG_CMD_MISC \
+)
+
+/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#if 0
+#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
+#else
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+#endif
+#define CONFIG_BOOTCOMMAND "" /* autoboot command */
+
+#define CONFIG_BOOTARGS "" /* */
+
+#define CONFIG_WATCHDOG /* turn on platform specific watchdog */
+
+/*#define CONFIG_STATUS_LED 1 *//* Enable status led */
+
+#define CONFIG_LOADS_ECHO 1 /* Echo on for serial download */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_CONSOLE_IS_IN_ENV /* stdin, stdout and stderr are in evironment */
+#define CONFIG_PREBOOT
+
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "pati=> " /* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x00010000 /* memtest works on */
+#define CFG_MEMTEST_END 0x00A00000 /* 10 MB in SRAM */
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+
+#define CFG_HZ 1000 /* Decrementer freq: 1 ms ticks */
+
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 1250000 }
+
+
+/***********************************************************************
+ * Last Stage Init
+ ***********************************************************************/
+#define CONFIG_LAST_STAGE_INIT
+
+/*
+ * Low Level Configuration Settings
+ */
+
+/*
+ * Internal Memory Mapped (This is not the IMMR content)
+ */
+#define CFG_IMMR 0x01C00000 /* Physical start adress of internal memory map */
+
+/*
+ * Definitions for initial stack pointer and data area
+ */
+#define CFG_INIT_RAM_ADDR (CFG_IMMR + 0x003f9800) /* Physical start adress of internal MPC555 writable RAM */
+#define CFG_INIT_RAM_END (CFG_IMMR + 0x003fffff) /* Physical end adress of internal MPC555 used RAM area */
+#define CFG_GBL_DATA_SIZE 128 /* Size in bytes reserved for initial global data */
+#define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_INIT_RAM_ADDR) - CFG_GBL_DATA_SIZE) /* Offset from the beginning of ram */
+#define CFG_INIT_SP_ADDR (CFG_IMMR + 0x03fa000) /* Physical start adress of inital stack */
+/*
+ * Start addresses for the final memory configuration
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE 0x00000000 /* Monitor won't change memory map */
+#define CFG_FLASH_BASE 0xffC00000 /* External flash */
+#define PCI_BASE 0x03000000 /* PCI Base (CS2) */
+#define PCI_CONFIG_BASE 0x04000000 /* PCI & PLD (CS3) */
+#define PLD_CONFIG_BASE 0x04001000 /* PLD (CS3) */
+
+#define CFG_MONITOR_BASE 0xFFF00000
+/* CFG_FLASH_BASE */ /* TEXT_BASE is defined in the board config.mk file. */
+ /* This adress is given to the linker with -Ttext to */
+ /* locate the text section at this adress. */
+#define CFG_MONITOR_LEN (256 << 10) /* Reserve 192 kB for Monitor */
+#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+
+
+
+#define CFG_RESET_ADDRESS (PLD_CONFIG_BASE + 0x10) /* Adress which causes reset */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ *-----------------------------------------------------------------------
+ *
+ */
+
+#define CFG_MAX_FLASH_BANKS 1 /* Max number of memory banks */
+#define CFG_MAX_FLASH_SECT 128 /* Max number of sectors on one chip */
+#define CFG_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 600 /* Timeout for Flash Write (in ms) */
+
+
+#define CFG_ENV_IS_IN_EEPROM
+#ifdef CFG_ENV_IS_IN_EEPROM
+#define CFG_ENV_OFFSET 0
+#define CFG_ENV_SIZE 2048
+#endif
+
+#undef CFG_ENV_IS_IN_FLASH
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SIZE 0x00002000 /* Set whole sector as env */
+#define CFG_ENV_OFFSET ((0 - CFG_FLASH_BASE) - CFG_ENV_SIZE) /* Environment starts at this adress */
+#endif
+
+
+#define CONFIG_SPI 1
+#define CFG_SPI_CS_USED 0x09 /* CS0 and CS3 are used */
+#define CFG_SPI_CS_BASE 0x08 /* CS3 is active low */
+#define CFG_SPI_CS_ACT 0x00 /* CS3 is active low */
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * SW Watchdog freeze
+ */
+#undef CONFIG_WATCHDOG
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+ SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+ SYPCR_SWP)
+#endif /* CONFIG_WATCHDOG */
+
+
+
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR (PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK SCCR_EBDF00
+#define CFG_SCCR (SCCR_TBS | SCCR_RTDIV | SCCR_RTSEL | \
+ SCCR_COM01 | SCCR_DFNL000 | SCCR_DFNH000)
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration
+ *-----------------------------------------------------------------------
+ * Data show cycle
+ */
+#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_EARB | SIUMCR_GPC01 | SIUMCR_MLRC11) /* Disable data show cycle */
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register
+ *-----------------------------------------------------------------------
+ * Set all bits to 40 Mhz
+ *
+ */
+#define CFG_OSC_CLK ((uint)4000000) /* Oscillator clock is 4MHz */
+
+
+#define CFG_PLPRCR (PLPRCR_MF_9 | PLPRCR_DIVF_0)
+
+/*-----------------------------------------------------------------------
+ * UMCR - UIMB Module Configuration Register
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_UMCR (UMCR_FSPEED) /* IMB clock same as U-bus */
+
+/*-----------------------------------------------------------------------
+ * ICTRL - I-Bus Support Control Register
+ */
+#define CFG_ICTRL (ICTRL_ISCT_SER_7) /* Take out of serialized mode */
+
+/*-----------------------------------------------------------------------
+ * USIU - Memory Controller Register
+ *-----------------------------------------------------------------------
+ */
+#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_V | BR_BI | BR_PS_16 | BR_SETA)
+#define CFG_OR0_PRELIM (0xffc00000) /* SCY is not used if external TA is set */
+/* SDRAM */
+#define CFG_BR1_PRELIM (CFG_SDRAM_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA)
+#define CFG_OR1_PRELIM (OR_ADDR_MK_FF) /* SCY is not used if external TA is set */
+/* PCI */
+#define CFG_BR2_PRELIM (PCI_BASE | BR_V | BR_PS_32 | BR_SETA)
+#define CFG_OR2_PRELIM (OR_ADDR_MK_FF)
+/* config registers: */
+#define CFG_BR3_PRELIM (PCI_CONFIG_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA)
+#define CFG_OR3_PRELIM (0xffff0000)
+
+#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* We don't realign the flash */
+
+/*-----------------------------------------------------------------------
+ * DER - Timer Decrementer
+ *-----------------------------------------------------------------------
+ * Initialise to zero
+ */
+#define CFG_DER 0x00000000
+
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+
+#define VERSION_TAG "released"
+#define CONFIG_ISO_STRING "MEV-10084-001"
+
+#define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG
+
+#endif /* __CONFIG_H */
diff --git a/include/mpc5xx.h b/include/mpc5xx.h
index 345fca8de3..7508f6df20 100644
--- a/include/mpc5xx.h
+++ b/include/mpc5xx.h
@@ -75,6 +75,10 @@
#define SIUMCR_DBPC01 0x00080000 /* - " - */
#define SIUMCR_DBPC10 0x00100000 /* - " - */
#define SIUMCR_DBPC11 0x00180000 /* - " - */
+#define SIUMCR_GPC00 0x00000000 /* General Pins Config */
+#define SIUMCR_GPC01 0x00020000 /* General Pins Config */
+#define SIUMCR_GPC10 0x00040000 /* General Pins Config */
+#define SIUMCR_GPC11 0x00060000 /* General Pins Config */
#define SIUMCR_DLK 0x00010000 /* Debug Register Lock */
#define SIUMCR_SC00 0x00000000 /* Multi Chip 32 bit */
#define SIUMCR_SC01 0x00004000 /* Muilt Chip 16 bit */
@@ -98,6 +102,7 @@
* PISCR - Periodic Interrupt Status and Control Register
*/
#define PISCR_PITF ((ushort)0x0002) /* PIT stops when FREEZE */
+#define PISCR_PS 0x0080 /* Periodic Interrupt Status */
/*-----------------------------------------------------------------------
* PLPRCR - PLL, Low-Power, and Reset Control Register
@@ -106,11 +111,12 @@
#define PLPRCR_DIVF_MSK 0x0000001f /* DIVF mask */
#define PLPRCR_CSRC_MSK 0x00000400 /* CSRC mask */
#define PLPRCR_MF_SHIFT 0x00000014 /* Multiplication factor shift value */
-#define PLPRCR_DIVF_0 0x00900000 /* Division factor 0 */
-#define PLPRCR_MF_9 0x00000000 /* Mulitipliaction factor 9 */
+#define PLPRCR_DIVF_0 0x00000000 /* Division factor 0 */
+#define PLPRCR_MF_9 0x00900000 /* Mulitipliaction factor 9 */
#define PLPRCR_TEXPS 0x00004000 /* TEXP Status */
#define PLPRCR_TMIST 0x00001000 /* Timers Interrupt Status */
#define PLPRCR_CSR 0x00000080 /* CheskStop Reset value */
+#define PLPRCR_SPLSS 0x00008000 /* SPLL Lock Status Sticky bit */
/*-----------------------------------------------------------------------
* SCCR - System Clock and reset Control Register
@@ -124,6 +130,7 @@
#define SCCR_TBS 0x02000000 /* Time Base Source */
#define SCCR_RTDIV 0x01000000 /* RTC Clock Divide */
#define SCCR_COM00 0x00000000 /* full strength CLKOUT output buffer */
+#define SCCR_COM01 0x20000000 /* half strength CLKOUT output buffer */
#define SCCR_DFNL000 0x00000000 /* Division by 2 (default = minimum) */
#define SCCR_DFNH000 0x00000000 /* Division by 1 (default = minimum) */
@@ -136,6 +143,7 @@
#define BR_PS_16 0x00000800 /* 16 bit port size */
#define BR_PS_32 0x00000000 /* 32 bit port size */
#define BR_LBDIR 0x00000008 /* Late burst data in progess */
+#define BR_SETA 0x00000004 /* External Data Acknowledge */
#define OR_SCY_3 0x00000030 /* 3 clock cycles wait states */
#define OR_SCY_1 0x00000000 /* 1 clock cycle wait state */
#define OR_SCY_8 0x00000080 /* 8 clock cycles wait states */
@@ -143,7 +151,7 @@
#define OR_BSCY 0x00000060 /* Burst beats length in clocks */
#define OR_ACS_10 0x00000600 /* Adress to chip-select setup */
#define OR_CSNT 0x00000800 /* Chip-select negotation time */
-#define OR_ETHR 0x00000000 /* Extended hold time on read */
+#define OR_ETHR 0x00000100 /* Extended hold time on read */
#define OR_ADDR_MK_FF 0xFF000000
#define OR_ADDR_MK_FFFF 0xFFFF0000
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