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| author | Wolfgang Denk <wd@denx.de> | 2010-07-16 23:15:01 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2010-07-16 23:15:01 +0200 |
| commit | b6c208ab1ebc2ac01e0029b8456210617ff67156 (patch) | |
| tree | 65c1252178febcb70a5fc75e67748ceec8fe96e5 /include | |
| parent | 16909f34b76e89871c0da528d6fe2ebf4e32231e (diff) | |
| parent | 9f43d7997e9c5395eed4eddd32cd75942896a412 (diff) | |
| download | talos-obmc-uboot-b6c208ab1ebc2ac01e0029b8456210617ff67156.tar.gz talos-obmc-uboot-b6c208ab1ebc2ac01e0029b8456210617ff67156.zip | |
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Diffstat (limited to 'include')
31 files changed, 518 insertions, 32 deletions
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index 9a40adc355..524afa5c6e 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -36,6 +36,7 @@ #define CONFIG_MPC8313ERDB 1 #define CONFIG_PCI +#define CONFIG_FSL_ELBC 1 #define CONFIG_MISC_INIT_R diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index 6972fe8cd1..f1b110b9d6 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -197,6 +197,7 @@ #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 #define CONFIG_SYS_LBC_LBCR 0x00040000 +#define CONFIG_FSL_ELBC 1 /* * FLASH on the Local Bus diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index b30d0e385a..9092755c6d 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -223,6 +223,7 @@ #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 #define CONFIG_SYS_LBC_LBCR 0x00000000 +#define CONFIG_FSL_ELBC 1 /* * FLASH on the Local Bus diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 1654f46a46..79dadc4a54 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -246,6 +246,7 @@ #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 #define CONFIG_SYS_LBC_LBCR 0x00000000 +#define CONFIG_FSL_ELBC 1 /* * FLASH on the Local Bus diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index da4313ac3a..a014ad0941 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -1,5 +1,5 @@ /* - * Copyright 2008-2009 Freescale Semiconductor, Inc. + * Copyright 2007-2009,2010 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -27,6 +27,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#include "../board/freescale/common/ics307_clk.h" + #ifdef CONFIG_MK_36BIT #define CONFIG_PHYS_64BIT 1 #endif @@ -70,15 +72,9 @@ #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE -#ifndef __ASSEMBLY__ -extern unsigned long get_board_sys_clk(unsigned long dummy); -extern unsigned long get_board_ddr_clk(unsigned long dummy); -#endif -#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ -#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ +#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ -#define CONFIG_GET_CLK_FROM_ICS307 /* decode sysclk and ddrclk freq - from ICS307 instead of switches */ /* * These can be toggled for performance analysis, otherwise use default. @@ -669,6 +665,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_CMD_ELF #define CONFIG_CMD_IRQ #define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_REGINFO #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI diff --git a/include/configs/MPC8540EVAL.h b/include/configs/MPC8540EVAL.h index 95ea275839..7daf934d02 100644 --- a/include/configs/MPC8540EVAL.h +++ b/include/configs/MPC8540EVAL.h @@ -294,6 +294,7 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_I2C +#define CONFIG_CMD_REGINFO #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index e945da2e6d..ae4fba8014 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -403,6 +403,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_CMD_ELF #define CONFIG_CMD_IRQ #define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_REGINFO #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index 799d9461f8..faba353119 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -420,6 +420,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_CMD_ELF #define CONFIG_CMD_IRQ #define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_REGINFO #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 3eb0049a04..fdd3597f79 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -462,6 +462,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_CMD_ELF #define CONFIG_CMD_IRQ #define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_REGINFO #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index 07a8e6126a..5011e5a8bf 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -401,6 +401,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_CMD_ELF #define CONFIG_CMD_IRQ #define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_REGINFO #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index 4a4a9eda85..98677e5f1b 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -416,6 +416,7 @@ #define CONFIG_CMD_ELF #define CONFIG_CMD_IRQ #define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_REGINFO #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index 6973538a8c..0cc2d47428 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -421,6 +421,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_CMD_ELF #define CONFIG_CMD_IRQ #define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_REGINFO #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 0c43b2b0c7..bb7bb47d65 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -539,6 +539,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_CMD_ELF #define CONFIG_CMD_IRQ #define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_REGINFO #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 78b73695bc..57c2f2f236 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -1,5 +1,5 @@ /* - * Copyright 2007-2008 Freescale Semiconductor, Inc. + * Copyright 2007-2008,2010 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -27,6 +27,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#include "../board/freescale/common/ics307_clk.h" + #ifdef CONFIG_MK_36BIT #define CONFIG_PHYS_64BIT #endif @@ -53,15 +55,9 @@ #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE -#ifndef __ASSEMBLY__ -extern unsigned long get_board_sys_clk(unsigned long dummy); -extern unsigned long get_board_ddr_clk(unsigned long dummy); -#endif -#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ -#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */ +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ +#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */ #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ -#define CONFIG_GET_CLK_FROM_ICS307 /* decode sysclk and ddrclk freq - from ICS307 instead of switches */ /* * These can be toggled for performance analysis, otherwise use default. @@ -574,6 +570,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_CMD_ELF #define CONFIG_CMD_IRQ #define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_REGINFO #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h new file mode 100644 index 0000000000..b42b5d09f1 --- /dev/null +++ b/include/configs/P1022DS.h @@ -0,0 +1,470 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> + * Timur Tabi <timur@freescale.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "../board/freescale/common/ics307_clk.h" + +/* High Level Configuration Options */ +#define CONFIG_BOOKE /* BOOKE */ +#define CONFIG_E500 /* BOOKE e500 family */ +#define CONFIG_MPC85xx /* MPC8540/60/55/41/48 */ +#define CONFIG_P1022 +#define CONFIG_P1022DS +#define CONFIG_MP /* support multiple processors */ + +#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ +#define CONFIG_PCI /* Enable PCI/PCIE */ +#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ +#define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */ +#define CONFIG_PCIE3 /* PCIE controler 3 (ULI bridge) */ +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ + +#define CONFIG_PHYS_64BIT +#define CONFIG_ENABLE_36BIT_PHYS +#define CONFIG_ADDR_MAP +#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ + +#define CONFIG_FSL_LAW /* Use common FSL init code */ + +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() +#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() +#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_L2_CACHE +#define CONFIG_BTB + +#define CONFIG_SYS_MEMTEST_START 0x00000000 +#define CONFIG_SYS_MEMTEST_END 0x7fffffff + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ +#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull +#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR + +#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR + 0x9000) /* pci0 */ +#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR + 0xa000) /* pci1 */ +#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR + 0xb000) /* pci2 */ + +/* DDR Setup */ +#define CONFIG_DDR_SPD +#define CONFIG_VERY_BIG_RAM +#define CONFIG_FSL_DDR3 + +#ifdef CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#endif + +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) + +/* I2C addresses of SPD EEPROMs */ +#define CONFIG_SYS_SPD_BUS_NUM 1 +#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ + +/* + * Memory map + * + * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable + * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable + * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable + * + * Localbus cacheable (TBD) + * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable + * + * Localbus non-cacheable + * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable + * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable + * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 + * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 + * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable + */ + +/* + * Local Bus Definitions + */ +#define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ +#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull + +#define CONFIG_FLASH_BR_PRELIM \ + (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V) +#define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7) + +#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ +#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ + +#define CONFIG_SYS_BR1_PRELIM \ + (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) +#define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM + +#define CONFIG_SYS_FLASH_BANKS_LIST \ + {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 2 +#define CONFIG_SYS_MAX_FLASH_SECT 1024 + +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_EMPTY_INFO + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_EARLY_INIT_R +#define CONFIG_MISC_INIT_R + +#define CONFIG_FSL_NGPIXIS +#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ +#define PIXIS_BASE_PHYS 0xfffdf0000ull + +#define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) +#define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | 0x6ff7) + +#define PIXIS_LBMAP_SWITCH 7 +#define PIXIS_LBMAP_MASK 0xE0 +#define PIXIS_LBMAP_ALTBANK 0x20 + +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ +#define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ + +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET \ + (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +#define CONFIG_FSL_DIU_FB +#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000) + +/* Video */ +/* #define CONFIG_VIDEO */ +#ifdef CONFIG_VIDEO +#define CONFIG_CFB_CONSOLE +#define CONFIG_VGA_AS_SINGLE_DEVICE +#endif + +/* + * Pass open firmware flat tree + */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_OF_STDOUT_VIA_ALIAS + +/* new uImage format support */ +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE + +/* I2C */ +#define CONFIG_FSL_I2C +#define CONFIG_HARD_I2C +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_SYS_I2C_SPEED 400000 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} +#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C2_OFFSET 0x3100 + +/* + * I2C2 EEPROM + */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_BUS_NUM 1 + +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ + +/* controller 1, Slot 2, tgtid 1, Base address a000 */ +#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ + +/* controller 2, direct to uli, tgtid 2, Base address 9000 */ +#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ + +/* controller 3, Slot 1, tgtid 3, Base address b000 */ +#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ + +#ifdef CONFIG_PCI +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#endif + +/* SATA */ +#define CONFIG_LIBATA +#define CONFIG_FSL_SATA + +#define CONFIG_SYS_SATA_MAX_DEVICE 2 +#define CONFIG_SATA1 +#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR +#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA +#define CONFIG_SATA2 +#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR +#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA + +#ifdef CONFIG_FSL_SATA +#define CONFIG_LBA48 +#define CONFIG_CMD_SATA +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_EXT2 +#endif + +#define CONFIG_MMC +#ifdef CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_GENERIC_MMC +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#endif + +#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + +#define CONFIG_TSEC_ENET +#ifdef CONFIG_TSEC_ENET + +#define CONFIG_TSECV2 +#define CONFIG_NET_MULTI + +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC1" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "eTSEC2" + +#define TSEC1_PHY_ADDR 1 +#define TSEC2_PHY_ADDR 2 + +#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) + +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 + +#define CONFIG_ETHPRIME "eTSEC1" + +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ +#endif + +/* + * Environment + */ +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_OVERWRITE +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x20000 + +#define CONFIG_LOADS_ECHO +#define CONFIG_SYS_LOADS_BAUD_CHANGE + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_ELF +#define CONFIG_CMD_ERRATA +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_SETEXPR + +#ifdef CONFIG_PCI +#define CONFIG_CMD_PCI +#define CONFIG_CMD_NET +#endif + +/* + * USB + */ +#define CONFIG_USB_EHCI + +#ifdef CONFIG_USB_EHCI +#define CONFIG_CMD_USB +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_EHCI_FSL +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_FAT +#endif + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#ifdef CONFIG_CMD_KGDB +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_HZ 1000 + +/* + * For booting Linux, the board info and command line data + * have to be in the first 16 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ + +#define CONFIG_HOSTNAME p1022ds +#define CONFIG_ROOTPATH /opt/nfsroot +#define CONFIG_BOOTFILE uImage +#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ + +#define CONFIG_LOADADDR 1000000 + +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ +#define CONFIG_BOOTARGS + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "perf_mode=stable\0" \ + "memctl_intlv_ctl=2\0" \ + "netdev=eth0\0" \ + "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot; " \ + "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ + "erase " MK_STR(TEXT_BASE) " +$filesize; " \ + "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ + "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ + "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=uramdisk\0" \ + "fdtaddr=c00000\0" \ + "fdtfile=p1022ds.dtb\0" \ + "bdev=sda3\0" \ + "diuregs=md e002c000 1d\0" \ + "dium=mw e002c01c\0" \ + "diuerr=md e002c014 1\0" \ + "othbootargs=diufb=15M video=fslfb:1280x1024-32@60,monitor=0 tty0\0" \ + "monitor=0-DVI\0" + +#define CONFIG_HDBOOT \ + "setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND + +#endif diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index b891730789..3cebbab53c 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -74,6 +74,7 @@ #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE +#define CONFIG_E1000 1 /* E1000 pci Ethernet card*/ #ifndef __ASSEMBLY__ extern unsigned long get_board_sys_clk(unsigned long dummy); #endif @@ -84,6 +85,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_MP #endif +#define CONFIG_HWCONFIG + /* * These can be toggled for performance analysis, otherwise use default. */ @@ -475,6 +478,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_CMD_MII #define CONFIG_CMD_PING #define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_REGINFO #if defined(CONFIG_PCI) #define CONFIG_CMD_NET diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index 66be725c8a..569da4f645 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -1,5 +1,5 @@ /* - * Copyright 2007-2009 Freescale Semiconductor, Inc. + * Copyright 2007-2010 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -27,6 +27,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#include "../board/freescale/common/ics307_clk.h" + #ifdef CONFIG_MK_36BIT #define CONFIG_PHYS_64BIT #endif @@ -54,17 +56,9 @@ #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE -#ifndef __ASSEMBLY__ -extern unsigned long calculate_board_sys_clk(unsigned long dummy); -extern unsigned long calculate_board_ddr_clk(unsigned long dummy); -/* extern unsigned long get_board_sys_clk(unsigned long dummy); */ -/* extern unsigned long get_board_ddr_clk(unsigned long dummy); */ -#endif -#define CONFIG_SYS_CLK_FREQ calculate_board_sys_clk(0) /* sysclk for MPC85xx */ -#define CONFIG_DDR_CLK_FREQ calculate_board_ddr_clk(0) /* ddrclk for MPC85xx */ +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ +#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */ #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ -#define CONFIG_GET_CLK_FROM_ICS307 /* decode sysclk and ddrclk freq - from ICS307 instead of switches */ /* * These can be toggled for performance analysis, otherwise use default. @@ -553,6 +547,7 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy); #define CONFIG_CMD_ELF #define CONFIG_CMD_IRQ #define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_REGINFO #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI diff --git a/include/configs/PM854.h b/include/configs/PM854.h index 4b9bcca79b..7426bcadfd 100644 --- a/include/configs/PM854.h +++ b/include/configs/PM854.h @@ -326,6 +326,7 @@ #define CONFIG_CMD_MII #define CONFIG_CMD_DATE #define CONFIG_CMD_EEPROM +#define CONFIG_CMD_REGINFO #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI diff --git a/include/configs/PM856.h b/include/configs/PM856.h index 1db20bcceb..0bd28fc8ce 100644 --- a/include/configs/PM856.h +++ b/include/configs/PM856.h @@ -325,6 +325,7 @@ #define CONFIG_CMD_I2C #define CONFIG_CMD_DATE #define CONFIG_CMD_EEPROM +#define CONFIG_CMD_REGINFO #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h index 1989e5aea6..5d424dd75f 100644 --- a/include/configs/SBC8540.h +++ b/include/configs/SBC8540.h @@ -380,6 +380,7 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_I2C +#define CONFIG_CMD_REGINFO #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI diff --git a/include/configs/SIMPC8313.h b/include/configs/SIMPC8313.h index eb8657b6be..70b7489ab1 100644 --- a/include/configs/SIMPC8313.h +++ b/include/configs/SIMPC8313.h @@ -37,6 +37,7 @@ #define CONFIG_MPC8313 1 #define CONFIG_PCI +#define CONFIG_FSL_ELBC 1 #define CONFIG_MISC_INIT_R diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index d44fb07cc0..90abe14f24 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -593,6 +593,7 @@ #define CONFIG_CMD_EEPROM #define CONFIG_CMD_DTT #define CONFIG_CMD_MII +#define CONFIG_CMD_REGINFO #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI diff --git a/include/configs/XPEDITE5200.h b/include/configs/XPEDITE5200.h index 1a56c6076b..df5ef78489 100644 --- a/include/configs/XPEDITE5200.h +++ b/include/configs/XPEDITE5200.h @@ -338,6 +338,7 @@ #define CONFIG_CMD_PCI #define CONFIG_CMD_PING #define CONFIG_CMD_SNTP +#define CONFIG_CMD_REGINFO /* * Miscellaneous configurable options diff --git a/include/configs/XPEDITE5370.h b/include/configs/XPEDITE5370.h index 7fd3668b20..1d6091caf6 100644 --- a/include/configs/XPEDITE5370.h +++ b/include/configs/XPEDITE5370.h @@ -47,6 +47,7 @@ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ +#define CONFIG_FSL_ELBC 1 /* * Multicore config @@ -396,6 +397,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_CMD_PING #define CONFIG_CMD_SAVEENV #define CONFIG_CMD_SNTP +#define CONFIG_CMD_REGINFO /* * Miscellaneous configurable options diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index aeac2dea3e..3f4056e82b 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -487,6 +487,7 @@ #define CONFIG_CMD_I2C #define CONFIG_CMD_MII #define CONFIG_CMD_ELF +#define CONFIG_CMD_REGINFO #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h index dab4f801d8..53d06ed698 100644 --- a/include/configs/sbc8560.h +++ b/include/configs/sbc8560.h @@ -382,6 +382,7 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_I2C +#define CONFIG_CMD_REGINFO #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 89f7cc4a19..ad7010900d 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -355,6 +355,7 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_SNTP #define CONFIG_CMD_USB +#define CONFIG_CMD_REGINFO #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h index 86b231ca8e..891d2bfb3b 100644 --- a/include/configs/stxgp3.h +++ b/include/configs/stxgp3.h @@ -321,6 +321,7 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_I2C +#define CONFIG_CMD_REGINFO #if defined(CONFIG_SYS_RAMBOOT) #undef CONFIG_CMD_SAVEENV diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h index 2783f9e04e..363f7b473a 100644 --- a/include/configs/stxssa.h +++ b/include/configs/stxssa.h @@ -353,6 +353,7 @@ #define CONFIG_CMD_NFS #define CONFIG_CMD_PING #define CONFIG_CMD_SNTP +#define CONFIG_CMD_REGINFO #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI diff --git a/include/fdt_support.h b/include/fdt_support.h index 9a453af34b..fc16159eb2 100644 --- a/include/fdt_support.h +++ b/include/fdt_support.h @@ -59,7 +59,7 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd); static inline void fdt_fixup_dr_usb(void *blob, bd_t *bd) {} #endif /* CONFIG_HAS_FSL_DR_USB */ -#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC83xx) +#if defined(CONFIG_SYS_FSL_SEC_COMPAT) void fdt_fixup_crypto_node(void *blob, int sec_rev); #else static inline void fdt_fixup_crypto_node(void *blob, int sec_rev) {} diff --git a/include/mpc85xx.h b/include/mpc85xx.h index a4d4d65526..2495b99c31 100644 --- a/include/mpc85xx.h +++ b/include/mpc85xx.h @@ -6,8 +6,6 @@ #ifndef __MPC85xx_H__ #define __MPC85xx_H__ -#include <asm/fsl_lbc.h> - /* define for common ppc_asm.tmpl */ #define EXC_OFF_SYS_RESET 0x100 /* System reset */ #define _START_OFFSET 0 |
