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| author | Kumar Gala <galak@kernel.crashing.org> | 2008-08-26 15:01:37 -0500 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2008-08-27 02:06:04 +0200 |
| commit | 9bd4e5911b750837515466bc7449087698b88e0e (patch) | |
| tree | d6f80cff80369b09a932ac4c5509b3c9fd91a266 /include | |
| parent | 39aa1a73483e1ac2bd56d5523abfc3970ee82c77 (diff) | |
| download | talos-obmc-uboot-9bd4e5911b750837515466bc7449087698b88e0e.tar.gz talos-obmc-uboot-9bd4e5911b750837515466bc7449087698b88e0e.zip | |
FSL DDR: Convert SBC8641D to new DDR code.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/sbc8641d.h | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h index efc787e999..ddca527c4e 100644 --- a/include/configs/sbc8641d.h +++ b/include/configs/sbc8641d.h @@ -61,8 +61,6 @@ #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ #undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup*/ -#undef CONFIG_DDR_DLL /* possible DLL fix needed */ -#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ #undef CONFIG_DDR_ECC /* only for ECC DDR module */ #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef @@ -114,6 +112,10 @@ #define MPC86xx_DDR_SDRAM_CLK_CNTL +#define CONFIG_NUM_DDR_CONTROLLERS 2 +#define CONFIG_DIMM_SLOTS_PER_CTLR 2 +#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) + #if defined(CONFIG_SPD_EEPROM) /* * Determine DDR configuration from I2C interface. |
