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| author | Kumar Gala <galak@kernel.crashing.org> | 2008-06-06 13:12:18 -0500 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2008-08-27 11:43:48 -0500 |
| commit | 9617c8d49a21703eaf13a4033ab1a56eecc033cc (patch) | |
| tree | 82d74807cf979a8848774b8593c4a7f1d2906672 /include | |
| parent | 2a6c2d7ab2a66660f40a6cd3de2eb29ee29d9693 (diff) | |
| download | talos-obmc-uboot-9617c8d49a21703eaf13a4033ab1a56eecc033cc.tar.gz talos-obmc-uboot-9617c8d49a21703eaf13a4033ab1a56eecc033cc.zip | |
FSL DDR: Convert MPC8540ADS to new DDR code.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/MPC8540ADS.h | 53 |
1 files changed, 23 insertions, 30 deletions
diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 6351925d7b..74f860536e 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -48,13 +48,6 @@ #define CONFIG_PCI #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ -#define CONFIG_DDR_DLL /* possible DLL fix needed */ -#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ - -#define CONFIG_DDR_ECC /* only for ECC DDR module */ -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ /* @@ -100,33 +93,33 @@ #define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ +/* DDR Setup */ +#define CONFIG_FSL_DDR1 +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ +#define CONFIG_DDR_SPD +#undef CONFIG_FSL_DDR_INTERACTIVE + +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef -/* - * DDR Setup - */ #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE -#if defined(CONFIG_SPD_EEPROM) - /* - * Determine DDR configuration from I2C interface. - */ - #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ - -#else - /* - * Manually set up DDR parameters - */ - #define CFG_SDRAM_SIZE 128 /* DDR is 128MB */ - #define CFG_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ - #define CFG_DDR_CS0_CONFIG 0x80000002 - #define CFG_DDR_TIMING_1 0x37344321 - #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ - #define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ - #define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ - #define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ -#endif - +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) + +/* I2C addresses of SPD EEPROMs */ +#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ + +/* These are used when DDR doesn't use SPD. */ +#define CFG_SDRAM_SIZE 128 /* DDR is 128MB */ +#define CFG_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ +#define CFG_DDR_CS0_CONFIG 0x80000002 +#define CFG_DDR_TIMING_1 0x37344321 +#define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ +#define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ +#define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ +#define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ /* * SDRAM on the Local Bus |
