diff options
| author | Paul Gortmaker <paul.gortmaker@windriver.com> | 2011-12-30 23:53:12 -0500 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2012-01-11 13:59:14 -0600 |
| commit | 3e3262bd149e21d0f5a82648218c26f2aa0e15e7 (patch) | |
| tree | 954100513b29dbcea5804303864c74d75ba729b0 /include | |
| parent | 2a6b3b74d85cff3f9a76edd09a7b2e8e25bb4eb4 (diff) | |
| download | talos-obmc-uboot-3e3262bd149e21d0f5a82648218c26f2aa0e15e7.tar.gz talos-obmc-uboot-3e3262bd149e21d0f5a82648218c26f2aa0e15e7.zip | |
sbc8548: enable support for hardware SPD errata workaround
Existing boards by default have an issue where the LBC SDRAM
SPD EEPROM and the DDR2 SDRAM SPD EEPROM both land at 0x51.
After the hardware modification listed in the README is made,
then the DDR2 SPD EEPROM appears at 0x53. So this implements
a board specific get_spd() by taking advantage of the existing
weak linkage, that 1st tries reading at 0x53 and then if that
fails, it falls back to the old 0x51.
Since the old dependency issue of "SPD implies no LBC SDRAM"
gets removed with the hardware errata fix, remove that restriction
in the code, so both LBC SDRAM and SPD can be selected.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/sbc8548.h | 14 |
1 files changed, 10 insertions, 4 deletions
diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index 09245b5b0c..d87394c8d1 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -124,7 +124,9 @@ * A hardware errata caused the LBC SDRAM SPD and the DDR2 SPD * to collide, meaning you couldn't reliably read either. So * physically remove the LBC PC100 SDRAM module from the board - * before enabling the two SPD options below. + * before enabling the two SPD options below, or check that you + * have the hardware fix on your board via "i2c probe" and looking + * for a device at 0x53. */ #undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #undef CONFIG_DDR_SPD @@ -140,8 +142,13 @@ #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 -/* I2C addresses of SPD EEPROMs */ +/* + * The hardware fix for the I2C address collision puts the DDR + * SPD at 0x53, but if we are running on an older board w/o the + * fix, it will still be at 0x51. We check 0x53 1st. + */ #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ +#define ALT_SPD_EEPROM_ADDRESS 0x53 /* CTLR 0 DIMM 0 */ /* * Make sure required options are set @@ -293,11 +300,10 @@ * Note that most boards have a hardware errata where both the * LBC SDRAM and the DDR2 SDRAM decode at 0x51, making it impossible * to use CONFIG_DDR_SPD unless you physically remove the LBC DIMM. + * A hardware workaround is also available, see README.sbc8548 file. */ -#ifndef CONFIG_DDR_SPD #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ #define CONFIG_SYS_LBC_SDRAM_SIZE 128 /* LBC SDRAM is 128MB */ -#endif /* * Base Register 3 and Option Register 3 configure the 1st 1/2 SDRAM. |
