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| author | Kumar Gala <galak@kernel.crashing.org> | 2008-08-26 23:15:28 -0500 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2008-08-27 11:43:51 -0500 |
| commit | 33b9079ba20926f14238fff863b68a98e938948e (patch) | |
| tree | f9d7bed6f7f2710a18647a57e909f83e1796a509 /include | |
| parent | a947e4c7eb15cea1d9fb633955c516aab5ad35dd (diff) | |
| download | talos-obmc-uboot-33b9079ba20926f14238fff863b68a98e938948e.tar.gz talos-obmc-uboot-33b9079ba20926f14238fff863b68a98e938948e.zip | |
FSL DDR: Convert sbc8548 to new DDR code.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/sbc8548.h | 31 |
1 files changed, 18 insertions, 13 deletions
diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index b4238e566f..9ef0bfdd86 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -47,19 +47,11 @@ #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE -#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ -#define CONFIG_DDR_DLL /* possible DLL fix needed */ -#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ -#undef CONFIG_DDR_ECC /* only for ECC DDR module */ -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ -#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */ - #define CONFIG_SYS_CLK_FREQ 66000000 /* SBC8548 default SYSCLK */ /* @@ -94,13 +86,26 @@ #define CFG_PCI2_ADDR (CFG_CCSRBAR+0x9000) #define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000) -/* - * DDR Setup - */ -#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +/* DDR Setup */ +#define CONFIG_FSL_DDR2 +#undef CONFIG_FSL_DDR_INTERACTIVE +#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ +#undef CONFIG_DDR_SPD +#undef CONFIG_DDR_ECC /* only for ECC DDR module */ + +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef + +#define CFG_DDR_SDRAM_BASE 0x00000000 #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE +#define CONFIG_VERY_BIG_RAM + +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL 2 -#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ +/* I2C addresses of SPD EEPROMs */ +#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ /* * Make sure required options are set |
