Merge branch 'master' of git://git.denx.de/u-boot-i2c

12 files changed, 602 insertions, 43 deletions

diff --git a/include/asm-arm/arch-nomadik/gpio.h b/include/asm-arm/arch-nomadik/gpio.h
new file mode 100644
index 0000000000..1d3c9ce0ab
--- /dev/null
+++ b/include/asm-arm/arch-nomadik/gpio.h
@@ -0,0 +1,42 @@
+/*
+ * (C) Copyright 2009 Alessandro Rubini
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __NMK_GPIO_H__
+#define __NMK_GPIO_H__
+
+/*
+ * These functions are called from the soft-i2c driver, but
+ * are also used by board files to set output bits.
+ */
+
+enum nmk_af { /* alternate function settings */
+	GPIO_GPIO = 0,
+	GPIO_ALT_A,
+	GPIO_ALT_B,
+	GPIO_ALT_C
+};
+
+extern void nmk_gpio_af(int gpio, int alternate_function);
+extern void nmk_gpio_dir(int gpio, int dir);
+extern void nmk_gpio_set(int gpio, int val);
+extern int nmk_gpio_get(int gpio);
+
+#endif /* __NMK_GPIO_H__ */
diff --git a/include/asm-arm/arch-omap24xx/i2c.h b/include/asm-arm/arch-omap24xx/i2c.h
index 7248950e52..44db7a2d45 100644
--- a/include/asm-arm/arch-omap24xx/i2c.h
+++ b/include/asm-arm/arch-omap24xx/i2c.h
@@ -104,4 +104,48 @@
 #define I2C_SYSTEST_SDA_I       (1 << 1)        /* SDA line sense input value */
 #define I2C_SYSTEST_SDA_O       (1 << 0)        /* SDA line drive output value */
 
+/* These values were copied from omap3, include/asm-arm/arch-omap3/i2c.h. */
+#define OMAP_I2C_STANDARD		100000
+#define OMAP_I2C_FAST_MODE		400000
+#define OMAP_I2C_HIGH_SPEED		3400000
+
+#define SYSTEM_CLOCK_12			12000000
+#define SYSTEM_CLOCK_13			13000000
+#define SYSTEM_CLOCK_192		19200000
+#define SYSTEM_CLOCK_96			96000000
+
+#ifndef I2C_IP_CLK
+#define I2C_IP_CLK			SYSTEM_CLOCK_96
+#endif
+
+#ifndef I2C_INTERNAL_SAMPLING_CLK
+#define I2C_INTERNAL_SAMPLING_CLK	19200000
+#endif
+
+/* These are the trim values for standard and fast speed */
+#ifndef I2C_FASTSPEED_SCLL_TRIM
+#define I2C_FASTSPEED_SCLL_TRIM		6
+#endif
+#ifndef I2C_FASTSPEED_SCLH_TRIM
+#define I2C_FASTSPEED_SCLH_TRIM		6
+#endif
+
+/* These are the trim values for high speed */
+#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM
+#define I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM	I2C_FASTSPEED_SCLL_TRIM
+#endif
+#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM
+#define I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM	I2C_FASTSPEED_SCLH_TRIM
+#endif
+#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM
+#define I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM	I2C_FASTSPEED_SCLL_TRIM
+#endif
+#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM
+#define I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM	I2C_FASTSPEED_SCLH_TRIM
+#endif
+
+#define I2C_PSC_MAX			0x0f
+#define I2C_PSC_MIN			0x00
+
+
 #endif
diff --git a/include/asm-arm/arch-omap3/i2c.h b/include/asm-arm/arch-omap3/i2c.h
index 3937f35256..8b339cce9a 100644
--- a/include/asm-arm/arch-omap3/i2c.h
+++ b/include/asm-arm/arch-omap3/i2c.h
@@ -112,16 +112,72 @@
 #define I2C_SCLH_HSSCLH		8
 #define I2C_SCLH_HSSCLH_M	0xFF
 
-#define OMAP_I2C_STANDARD	100
-#define OMAP_I2C_FAST_MODE	400
-#define OMAP_I2C_HIGH_SPEED	3400
+#define OMAP_I2C_STANDARD	100000
+#define OMAP_I2C_FAST_MODE	400000
+#define OMAP_I2C_HIGH_SPEED	3400000
 
-#define SYSTEM_CLOCK_12		12000
-#define SYSTEM_CLOCK_13		13000
-#define SYSTEM_CLOCK_192	19200
-#define SYSTEM_CLOCK_96		96000
+#define SYSTEM_CLOCK_12		12000000
+#define SYSTEM_CLOCK_13		13000000
+#define SYSTEM_CLOCK_192	19200000
+#define SYSTEM_CLOCK_96		96000000
 
+/* Use the reference value of 96MHz if not explicitly set by the board */
+#ifndef I2C_IP_CLK
 #define I2C_IP_CLK		SYSTEM_CLOCK_96
+#endif
+
+/*
+ * The reference minimum clock for high speed is 19.2MHz.
+ * The linux 2.6.30 kernel uses this value.
+ * The reference minimum clock for fast mode is 9.6MHz
+ * The reference minimum clock for standard mode is 4MHz
+ * In TRM, the value of 12MHz is used.
+ */
+#ifndef I2C_INTERNAL_SAMPLING_CLK
+#define I2C_INTERNAL_SAMPLING_CLK	19200000
+#endif
+
+/*
+ * The equation for the low and high time is
+ * tlow = scll + scll_trim = (sampling clock * tlow_duty) / speed
+ * thigh = sclh + sclh_trim = (sampling clock * (1 - tlow_duty)) / speed
+ *
+ * If the duty cycle is 50%
+ *
+ * tlow = scll + scll_trim = sampling clock / (2 * speed)
+ * thigh = sclh + sclh_trim = sampling clock / (2 * speed)
+ *
+ * In TRM
+ * scll_trim = 7
+ * sclh_trim = 5
+ *
+ * The linux 2.6.30 kernel uses
+ * scll_trim = 6
+ * sclh_trim = 6
+ *
+ * These are the trim values for standard and fast speed
+ */
+#ifndef I2C_FASTSPEED_SCLL_TRIM
+#define I2C_FASTSPEED_SCLL_TRIM		6
+#endif
+#ifndef I2C_FASTSPEED_SCLH_TRIM
+#define I2C_FASTSPEED_SCLH_TRIM		6
+#endif
+
+/* These are the trim values for high speed */
+#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM
+#define I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM	I2C_FASTSPEED_SCLL_TRIM
+#endif
+#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM
+#define I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM	I2C_FASTSPEED_SCLH_TRIM
+#endif
+#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM
+#define I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM	I2C_FASTSPEED_SCLL_TRIM
+#endif
+#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM
+#define I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM	I2C_FASTSPEED_SCLH_TRIM
+#endif
+
 #define I2C_PSC_MAX		0x0f
 #define I2C_PSC_MIN		0x00
 
diff --git a/include/asm-arm/arch-omap3/omap3.h b/include/asm-arm/arch-omap3/omap3.h
index 7c1101969c..fa8f46d7f2 100644
--- a/include/asm-arm/arch-omap3/omap3.h
+++ b/include/asm-arm/arch-omap3/omap3.h
@@ -181,39 +181,4 @@ typedef struct gpio {
 #define WIDTH_8BIT		0x0000
 #define WIDTH_16BIT		0x1000	/* bit pos for 16 bit in gpmc */
 
-/* I2C power management companion definitions */
-#define PWRMGT_ADDR_ID1		0x48
-#define PWRMGT_ADDR_ID2		0x49
-#define PWRMGT_ADDR_ID3		0x4A
-#define PWRMGT_ADDR_ID4		0x4B
-
-/* I2C ID3 (slave3) register */
-#define LEDEN			0xEE
-
-#define LEDAON			(0x1 << 0)
-#define LEDBON			(0x1 << 1)
-#define LEDAPWM			(0x1 << 4)
-#define LEDBPWM			(0x1 << 5)
-
-/* I2C ID4 (slave4) register */
-#define VAUX2_DEV_GRP		0x76
-#define VAUX2_DEDICATED		0x79
-#define VAUX3_DEV_GRP		0x7A
-#define VAUX3_DEDICATED		0x7D
-#define VMMC1_DEV_GRP		0x82
-#define VMMC1_DEDICATED		0x85
-#define VPLL2_DEV_GRP		0x8E
-#define VPLL2_DEDICATED		0x91
-#define VDAC_DEV_GRP		0x96
-#define VDAC_DEDICATED		0x99
-
-#define DEV_GRP_P1		0x20
-#define DEV_GRP_ALL		0xE0
-
-#define VAUX2_VSEL_28		0x09
-#define VAUX3_VSEL_28		0x03
-#define VPLL2_VSEL_18		0x05
-#define VDAC_VSEL_18		0x03
-#define VMMC1_VSEL_30		0x02
-
 #endif
diff --git a/include/configs/nhk8815.h b/include/configs/nhk8815.h
index 3e2e09fb83..8a83d924bb 100644
--- a/include/configs/nhk8815.h
+++ b/include/configs/nhk8815.h
@@ -93,7 +93,7 @@
 #define CONFIG_SYS_GBL_DATA_SIZE	128	/* for initial data */
 #define CONFIG_SYS_64BIT_VSPRINTF	/* mtd desires this */
 
-#define CONFIG_MISC_INIT_R	/* call misc_init_r during start up */
+#define BOARD_LATE_INIT		/* call board_late_init during start up */
 
 /* timing informazion */
 #define CONFIG_SYS_HZ		1000 /* Mandatory... */
@@ -110,6 +110,22 @@
 #define CONFIG_PL01x_PORTS	{ (void *)CFG_SERIAL0, (void *)CFG_SERIAL1 }
 #define CONFIG_PL011_CLOCK	48000000
 
+/* i2c, for the port extenders (uses gpio.c in board directory) */
+#ifndef __ASSEMBLY__
+#include <asm/arch/gpio.h>
+#define CONFIG_CMD_I2C
+#define CONFIG_SOFT_I2C
+#define CONFIG_SYS_I2C_SPEED	400000
+#define __SDA			63
+#define __SCL			62
+#define I2C_SDA(x)		nmk_gpio_set(__SDA, x)
+#define I2C_SCL(x)		nmk_gpio_set(__SCL, x)
+#define I2C_READ		(nmk_gpio_get(__SDA)!=0)
+#define I2C_ACTIVE		nmk_gpio_dir(__SDA, 1)
+#define I2C_TRISTATE		nmk_gpio_dir(__SDA, 0)
+#define I2C_DELAY     (udelay(2))
+#endif /* __ASSEMBLY__ */
+
 /* Ethernet */
 #define PCI_MEMORY_VADDR	0xe8000000
 #define PCI_IO_VADDR		0xee000000
diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
index a1a849e292..8fc6fb26c9 100644
--- a/include/configs/omap3_beagle.h
+++ b/include/configs/omap3_beagle.h
@@ -130,6 +130,12 @@
 #define CONFIG_DRIVER_OMAP34XX_I2C	1
 
 /*
+ * TWL4030
+ */
+#define CONFIG_TWL4030_POWER		1
+#define CONFIG_TWL4030_LED		1
+
+/*
  * Board NAND Info.
  */
 #define CONFIG_NAND_OMAP_GPMC
diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
index 3d9d72caf3..809198b0f8 100644
--- a/include/configs/omap3_evm.h
+++ b/include/configs/omap3_evm.h
@@ -128,6 +128,11 @@
 #define CONFIG_DRIVER_OMAP34XX_I2C	1
 
 /*
+ * TWL4030
+ */
+#define CONFIG_TWL4030_POWER		1
+
+/*
  * Board NAND Info.
  */
 #define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h
index 3bf798a400..c359c60b18 100644
--- a/include/configs/omap3_overo.h
+++ b/include/configs/omap3_overo.h
@@ -116,6 +116,12 @@
 #define CONFIG_DRIVER_OMAP34XX_I2C	1
 
 /*
+ * TWL4030
+ */
+#define CONFIG_TWL4030_POWER		1
+#define CONFIG_TWL4030_LED		1
+
+/*
  * Board NAND Info.
  */
 #define CONFIG_NAND_OMAP_GPMC
diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h
index d7e0ea1c44..d7b1cc1895 100644
--- a/include/configs/omap3_pandora.h
+++ b/include/configs/omap3_pandora.h
@@ -119,6 +119,12 @@
 #define CONFIG_DRIVER_OMAP34XX_I2C	1
 
 /*
+ * TWL4030
+ */
+#define CONFIG_TWL4030_POWER		1
+#define CONFIG_TWL4030_LED		1
+
+/*
  * Board NAND Info.
  */
 #define CONFIG_NAND_OMAP_GPMC
diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h
index 4034ea4291..676b425473 100644
--- a/include/configs/omap3_zoom1.h
+++ b/include/configs/omap3_zoom1.h
@@ -126,6 +126,12 @@
 #define CONFIG_DRIVER_OMAP34XX_I2C	1
 
 /*
+ * TWL4030
+ */
+#define CONFIG_TWL4030_POWER		1
+#define CONFIG_TWL4030_LED		1
+
+/*
  * Board NAND Info.
  */
 #define CONFIG_NAND_OMAP_GPMC
diff --git a/include/configs/omap3_zoom2.h b/include/configs/omap3_zoom2.h
index 701a296b3d..3f6f5451a3 100644
--- a/include/configs/omap3_zoom2.h
+++ b/include/configs/omap3_zoom2.h
@@ -147,6 +147,12 @@
 #define CONFIG_DRIVER_OMAP34XX_I2C	1
 
 /*
+ * TWL4030
+ */
+#define CONFIG_TWL4030_POWER		1
+#define CONFIG_TWL4030_LED		1
+
+/*
  * Board NAND Info.
  */
 #define CONFIG_NAND_OMAP_GPMC
diff --git a/include/twl4030.h b/include/twl4030.h
new file mode 100644
index 0000000000..f260ecb8b1
--- /dev/null
+++ b/include/twl4030.h
@@ -0,0 +1,401 @@
+/*
+ * Copyright (c) 2009 Wind River Systems, Inc.
+ * Tom Rix <Tom.Rix at windriver.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Derived from code on omapzoom, git://git.omapzoom.com/repo/u-boot.git
+ *
+ * Copyright (C) 2007-2009 Texas Instruments, Inc.
+ */
+
+#ifndef TWL4030_H
+#define TWL4030_H
+
+#include <common.h>
+#include <i2c.h>
+
+/* I2C chip addresses */
+
+/* USB */
+#define TWL4030_CHIP_USB				0x48
+/* AUD */
+#define TWL4030_CHIP_AUDIO_VOICE			0x49
+#define TWL4030_CHIP_GPIO				0x49
+#define TWL4030_CHIP_INTBR				0x49
+#define TWL4030_CHIP_PIH				0x49
+#define TWL4030_CHIP_TEST				0x49
+/* AUX */
+#define TWL4030_CHIP_KEYPAD				0x4a
+#define TWL4030_CHIP_MADC				0x4a
+#define TWL4030_CHIP_INTERRUPTS				0x4a
+#define TWL4030_CHIP_LED				0x4a
+#define TWL4030_CHIP_MAIN_CHARGE			0x4a
+#define TWL4030_CHIP_PRECHARGE				0x4a
+#define TWL4030_CHIP_PWM0				0x4a
+#define TWL4030_CHIP_PWM1				0x4a
+#define TWL4030_CHIP_PWMA				0x4a
+#define TWL4030_CHIP_PWMB				0x4a
+/* POWER */
+#define TWL4030_CHIP_BACKUP				0x4b
+#define TWL4030_CHIP_INT				0x4b
+#define TWL4030_CHIP_PM_MASTER				0x4b
+#define TWL4030_CHIP_PM_RECEIVER			0x4b
+#define TWL4030_CHIP_RTC				0x4b
+#define TWL4030_CHIP_SECURED_REG			0x4b
+
+/* Register base addresses */
+
+/* USB */
+#define TWL4030_BASEADD_USB				0x0000
+/* AUD */
+#define TWL4030_BASEADD_AUDIO_VOICE			0x0000
+#define TWL4030_BASEADD_GPIO				0x0098
+#define TWL4030_BASEADD_INTBR				0x0085
+#define TWL4030_BASEADD_PIH				0x0080
+#define TWL4030_BASEADD_TEST				0x004C
+/* AUX */
+#define TWL4030_BASEADD_INTERRUPTS			0x00B9
+#define TWL4030_BASEADD_LED				0x00EE
+#define TWL4030_BASEADD_MADC				0x0000
+#define TWL4030_BASEADD_MAIN_CHARGE			0x0074
+#define TWL4030_BASEADD_PRECHARGE			0x00AA
+#define TWL4030_BASEADD_PWM0				0x00F8
+#define TWL4030_BASEADD_PWM1				0x00FB
+#define TWL4030_BASEADD_PWMA				0x00EF
+#define TWL4030_BASEADD_PWMB				0x00F1
+#define TWL4030_BASEADD_KEYPAD				0x00D2
+/* POWER */
+#define TWL4030_BASEADD_BACKUP				0x0014
+#define TWL4030_BASEADD_INT				0x002E
+#define TWL4030_BASEADD_PM_MASTER			0x0036
+#define TWL4030_BASEADD_PM_RECIEVER			0x005B
+#define TWL4030_BASEADD_RTC				0x001C
+#define TWL4030_BASEADD_SECURED_REG			0x0000
+
+/*
+ * Power Management Master
+ */
+#define TWL4030_PM_MASTER_CFG_P1_TRANSITION		0x36
+#define TWL4030_PM_MASTER_CFG_P2_TRANSITION		0x37
+#define TWL4030_PM_MASTER_CFG_P3_TRANSITION		0x38
+#define TWL4030_PM_MASTER_CFG_P123_TRANSITION		0x39
+#define TWL4030_PM_MASTER_STS_BOOT			0x3A
+#define TWL4030_PM_MASTER_CFG_BOOT			0x3B
+#define TWL4030_PM_MASTER_SHUNDAN			0x3C
+#define TWL4030_PM_MASTER_BOOT_BCI			0x3D
+#define TWL4030_PM_MASTER_CFG_PWRANA1			0x3E
+#define TWL4030_PM_MASTER_CFG_PWRANA2			0x3F
+#define TWL4030_PM_MASTER_BGAP_TRIM			0x40
+#define TWL4030_PM_MASTER_BACKUP_MISC_STS		0x41
+#define TWL4030_PM_MASTER_BACKUP_MISC_CFG		0x42
+#define TWL4030_PM_MASTER_BACKUP_MISC_TST		0x43
+#define TWL4030_PM_MASTER_PROTECT_KEY			0x44
+#define TWL4030_PM_MASTER_STS_HW_CONDITIONS		0x45
+#define TWL4030_PM_MASTER_P1_SW_EVENTS			0x46
+#define TWL4030_PM_MASTER_P2_SW_EVENTS			0x47
+#define TWL4030_PM_MASTER_P3_SW_EVENTS			0x48
+#define TWL4030_PM_MASTER_STS_P123_STATE		0x49
+#define TWL4030_PM_MASTER_PB_CFG			0x4A
+#define TWL4030_PM_MASTER_PB_WORD_MSB			0x4B
+#define TWL4030_PM_MASTER_PB_WORD_LSB			0x4C
+#define TWL4030_PM_MASTER_SEQ_ADD_W2P			0x52
+#define TWL4030_PM_MASTER_SEQ_ADD_P2A			0x53
+#define TWL4030_PM_MASTER_SEQ_ADD_A2W			0x54
+#define TWL4030_PM_MASTER_SEQ_ADD_A2S			0x55
+#define TWL4030_PM_MASTER_SEQ_ADD_S2A12			0x56
+#define TWL4030_PM_MASTER_SEQ_ADD_S2A3			0x57
+#define TWL4030_PM_MASTER_SEQ_ADD_WARM			0x58
+#define TWL4030_PM_MASTER_MEMORY_ADDRESS		0x59
+#define TWL4030_PM_MASTER_MEMORY_DATA			0x5A
+#define TWL4030_PM_MASTER_SC_CONFIG			0x5B
+#define TWL4030_PM_MASTER_SC_DETECT1			0x5C
+#define TWL4030_PM_MASTER_SC_DETECT2			0x5D
+#define TWL4030_PM_MASTER_WATCHDOG_CFG			0x5E
+#define TWL4030_PM_MASTER_IT_CHECK_CFG			0x5F
+#define TWL4030_PM_MASTER_VIBRATOR_CFG			0x60
+#define TWL4030_PM_MASTER_DCDC_GLOBAL_CFG		0x61
+#define TWL4030_PM_MASTER_VDD1_TRIM1			0x62
+#define TWL4030_PM_MASTER_VDD1_TRIM2			0x63
+#define TWL4030_PM_MASTER_VDD2_TRIM1			0x64
+#define TWL4030_PM_MASTER_VDD2_TRIM2			0x65
+#define TWL4030_PM_MASTER_VIO_TRIM1			0x66
+#define TWL4030_PM_MASTER_VIO_TRIM2			0x67
+#define TWL4030_PM_MASTER_MISC_CFG			0x68
+#define TWL4030_PM_MASTER_LS_TST_A			0x69
+#define TWL4030_PM_MASTER_LS_TST_B			0x6A
+#define TWL4030_PM_MASTER_LS_TST_C			0x6B
+#define TWL4030_PM_MASTER_LS_TST_D			0x6C
+#define TWL4030_PM_MASTER_BB_CFG			0x6D
+#define TWL4030_PM_MASTER_MISC_TST			0x6E
+#define TWL4030_PM_MASTER_TRIM1				0x6F
+/* P[1-3]_SW_EVENTS */
+#define TWL4030_PM_MASTER_SW_EVENTS_STOPON_PWRON	(1 << 6)
+#define TWL4030_PM_MASTER_SW_EVENTS_STOPON_SYSEN	(1 << 5)
+#define TWL4030_PM_MASTER_SW_EVENTS_ENABLE_WARMRESET	(1 << 4)
+#define TWL4030_PM_MASTER_SW_EVENTS_LVL_WAKEUP		(1 << 3)
+#define TWL4030_PM_MASTER_SW_EVENTS_DEVACT		(1 << 2)
+#define TWL4030_PM_MASTER_SW_EVENTS_DEVSLP		(1 << 1)
+#define TWL4030_PM_MASTER_SW_EVENTS_DEVOFF		(1 << 0)
+
+/* Power Managment Receiver */
+#define TWL4030_PM_RECEIVER_SC_CONFIG			0x5B
+#define TWL4030_PM_RECEIVER_SC_DETECT1			0x5C
+#define TWL4030_PM_RECEIVER_SC_DETECT2			0x5D
+#define TWL4030_PM_RECEIVER_WATCHDOG_CFG		0x5E
+#define TWL4030_PM_RECEIVER_IT_CHECK_CFG		0x5F
+#define TWL4030_PM_RECEIVER_VIBRATOR_CFG		0x5F
+#define TWL4030_PM_RECEIVER_DC_TO_DC_CFG		0x61
+#define TWL4030_PM_RECEIVER_VDD1_TRIM1			0x62
+#define TWL4030_PM_RECEIVER_VDD1_TRIM2			0x63
+#define TWL4030_PM_RECEIVER_VDD2_TRIM1			0x64
+#define TWL4030_PM_RECEIVER_VDD2_TRIM2			0x65
+#define TWL4030_PM_RECEIVER_VIO_TRIM1			0x66
+#define TWL4030_PM_RECEIVER_VIO_TRIM2			0x67
+#define TWL4030_PM_RECEIVER_MISC_CFG			0x68
+#define TWL4030_PM_RECEIVER_LS_TST_A			0x69
+#define TWL4030_PM_RECEIVER_LS_TST_B			0x6A
+#define TWL4030_PM_RECEIVER_LS_TST_C			0x6B
+#define TWL4030_PM_RECEIVER_LS_TST_D			0x6C
+#define TWL4030_PM_RECEIVER_BB_CFG			0x6D
+#define TWL4030_PM_RECEIVER_MISC_TST			0x6E
+#define TWL4030_PM_RECEIVER_TRIM1			0x6F
+#define TWL4030_PM_RECEIVER_TRIM2			0x70
+#define TWL4030_PM_RECEIVER_DC_DC_TIMEOUT		0x71
+#define TWL4030_PM_RECEIVER_VAUX1_DEV_GRP		0x72
+#define TWL4030_PM_RECEIVER_VAUX1_TYPE			0x73
+#define TWL4030_PM_RECEIVER_VAUX1_REMAP			0x74
+#define TWL4030_PM_RECEIVER_VAUX1_DEDICATED		0x75
+#define TWL4030_PM_RECEIVER_VAUX2_DEV_GRP		0x76
+#define TWL4030_PM_RECEIVER_VAUX2_TYPE			0x77
+#define TWL4030_PM_RECEIVER_VAUX2_REMAP			0x78
+#define TWL4030_PM_RECEIVER_VAUX2_DEDICATED		0x79
+#define TWL4030_PM_RECEIVER_VAUX3_DEV_GRP		0x7A
+#define TWL4030_PM_RECEIVER_VAUX3_TYPE			0x7B
+#define TWL4030_PM_RECEIVER_VAUX3_REMAP			0x7C
+#define TWL4030_PM_RECEIVER_VAUX3_DEDICATED		0x7D
+#define TWL4030_PM_RECEIVER_VAUX4_DEV_GRP		0x7E
+#define TWL4030_PM_RECEIVER_VAUX4_TYPE			0x7F
+#define TWL4030_PM_RECEIVER_VAUX4_REMAP			0x80
+#define TWL4030_PM_RECEIVER_VAUX4_DEDICATED		0x81
+#define TWL4030_PM_RECEIVER_VMMC1_DEV_GRP		0x82
+#define TWL4030_PM_RECEIVER_VMMC1_TYPE			0x83
+#define TWL4030_PM_RECEIVER_VMMC1_REMAP			0x84
+#define TWL4030_PM_RECEIVER_VMMC1_DEDICATED		0x85
+#define TWL4030_PM_RECEIVER_VMMC2_DEV_GRP		0x86
+#define TWL4030_PM_RECEIVER_VMMC2_TYPE			0x87
+#define TWL4030_PM_RECEIVER_VMMC2_REMAP			0x88
+#define TWL4030_PM_RECEIVER_VMMC2_DEDICATED		0x89
+#define TWL4030_PM_RECEIVER_VPLL1_DEV_GRP		0x8A
+#define TWL4030_PM_RECEIVER_VPLL1_TYPE			0x8B
+#define TWL4030_PM_RECEIVER_VPLL1_REMAP			0x8C
+#define TWL4030_PM_RECEIVER_VPLL1_DEDICATED		0x8D
+#define TWL4030_PM_RECEIVER_VPLL2_DEV_GRP		0x8E
+#define TWL4030_PM_RECEIVER_VPLL2_TYPE			0x8F
+#define TWL4030_PM_RECEIVER_VPLL2_REMAP			0x90
+#define TWL4030_PM_RECEIVER_VPLL2_DEDICATED		0x91
+#define TWL4030_PM_RECEIVER_VSIM_DEV_GRP		0x92
+#define TWL4030_PM_RECEIVER_VSIM_TYPE			0x93
+#define TWL4030_PM_RECEIVER_VSIM_REMAP			0x94
+#define TWL4030_PM_RECEIVER_VSIM_DEDICATED		0x95
+#define TWL4030_PM_RECEIVER_VDAC_DEV_GRP		0x96
+#define TWL4030_PM_RECEIVER_VDAC_TYPE			0x97
+#define TWL4030_PM_RECEIVER_VDAC_REMAP			0x98
+#define TWL4030_PM_RECEIVER_VDAC_DEDICATED		0x99
+#define TWL4030_PM_RECEIVER_VINTANA1_DEV_GRP		0x9A
+#define TWL4030_PM_RECEIVER_VINTANA1_TYP		0x9B
+#define TWL4030_PM_RECEIVER_VINTANA1_REMAP		0x9C
+#define TWL4030_PM_RECEIVER_VINTANA1_DEDICATED		0x9D
+#define TWL4030_PM_RECEIVER_VINTANA2_DEV_GRP		0x9E
+#define TWL4030_PM_RECEIVER_VINTANA2_TYPE		0x9F
+#define TWL4030_PM_RECEIVER_VINTANA2_REMAP		0xA0
+#define TWL4030_PM_RECEIVER_VINTANA2_DEDICATED		0xA1
+#define TWL4030_PM_RECEIVER_VINTDIG_DEV_GRP		0xA2
+#define TWL4030_PM_RECEIVER_VINTDIG_TYPE		0xA3
+#define TWL4030_PM_RECEIVER_VINTDIG_REMAP		0xA4
+#define TWL4030_PM_RECEIVER_VINTDIG_DEDICATED		0xA5
+#define TWL4030_PM_RECEIVER_VIO_DEV_GRP			0xA6
+#define TWL4030_PM_RECEIVER_VIO_TYPE			0xA7
+#define TWL4030_PM_RECEIVER_VIO_REMAP			0xA8
+#define TWL4030_PM_RECEIVER_VIO_CFG			0xA9
+#define TWL4030_PM_RECEIVER_VIO_MISC_CFG		0xAA
+#define TWL4030_PM_RECEIVER_VIO_TEST1			0xAB
+#define TWL4030_PM_RECEIVER_VIO_TEST2			0xAC
+#define TWL4030_PM_RECEIVER_VIO_OSC			0xAD
+#define TWL4030_PM_RECEIVER_VIO_RESERVED		0xAE
+#define TWL4030_PM_RECEIVER_VIO_VSEL			0xAF
+#define TWL4030_PM_RECEIVER_VDD1_DEV_GRP		0xB0
+#define TWL4030_PM_RECEIVER_VDD1_TYPE			0xB1
+#define TWL4030_PM_RECEIVER_VDD1_REMAP			0xB2
+#define TWL4030_PM_RECEIVER_VDD1_CFG			0xB3
+#define TWL4030_PM_RECEIVER_VDD1_MISC_CFG		0xB4
+#define TWL4030_PM_RECEIVER_VDD1_TEST1			0xB5
+#define TWL4030_PM_RECEIVER_VDD1_TEST2			0xB6
+#define TWL4030_PM_RECEIVER_VDD1_OSC			0xB7
+#define TWL4030_PM_RECEIVER_VDD1_RESERVED		0xB8
+#define TWL4030_PM_RECEIVER_VDD1_VSEL			0xB9
+#define TWL4030_PM_RECEIVER_VDD1_VMODE_CFG		0xBA
+#define TWL4030_PM_RECEIVER_VDD1_VFLOOR			0xBB
+#define TWL4030_PM_RECEIVER_VDD1_VROOF			0xBC
+#define TWL4030_PM_RECEIVER_VDD1_STEP			0xBD
+#define TWL4030_PM_RECEIVER_VDD2_DEV_GRP		0xBE
+#define TWL4030_PM_RECEIVER_VDD2_TYPE			0xBF
+#define TWL4030_PM_RECEIVER_VDD2_REMAP			0xC0
+#define TWL4030_PM_RECEIVER_VDD2_CFG			0xC1
+#define TWL4030_PM_RECEIVER_VDD2_MISC_CFG		0xC2
+#define TWL4030_PM_RECEIVER_VDD2_TEST1			0xC3
+#define TWL4030_PM_RECEIVER_VDD2_TEST2			0xC4
+#define TWL4030_PM_RECEIVER_VDD2_OSC			0xC5
+#define TWL4030_PM_RECEIVER_VDD2_RESERVED		0xC6
+#define TWL4030_PM_RECEIVER_VDD2_VSEL			0xC7
+#define TWL4030_PM_RECEIVER_VDD2_VMODE_CFG		0xC8
+#define TWL4030_PM_RECEIVER_VDD2_VFLOOR			0xC9
+#define TWL4030_PM_RECEIVER_VDD2_VROOF			0xCA
+#define TWL4030_PM_RECEIVER_VDD2_STEP			0xCB
+#define TWL4030_PM_RECEIVER_VUSB1V5_DEV_GRP		0xCC
+#define TWL4030_PM_RECEIVER_VUSB1V5_TYPE		0xCD
+#define TWL4030_PM_RECEIVER_VUSB1V5_REMAP		0xCE
+#define TWL4030_PM_RECEIVER_VUSB1V8_DEV_GRP		0xCF
+#define TWL4030_PM_RECEIVER_VUSB1V8_TYPE		0xD0
+#define TWL4030_PM_RECEIVER_VUSB1V8_REMAP		0xD1
+#define TWL4030_PM_RECEIVER_VUSB3V1_DEV_GRP		0xD2
+#define TWL4030_PM_RECEIVER_VUSB3V1_TYPE		0xD3
+#define TWL4030_PM_RECEIVER_VUSB3V1_REMAP		0xD4
+#define TWL4030_PM_RECEIVER_VUSBCP_DEV_GRP		0xD5
+#define TWL4030_PM_RECEIVER_VUSBCP_TYPE			0xD6
+#define TWL4030_PM_RECEIVER_VUSBCP_REMAP		0xD7
+#define TWL4030_PM_RECEIVER_VUSB_DEDICATED1		0xD8
+#define TWL4030_PM_RECEIVER_VUSB_DEDICATED2		0xD9
+#define TWL4030_PM_RECEIVER_REGEN_DEV_GRP		0xDA
+#define TWL4030_PM_RECEIVER_REGEN_TYPE			0xDB
+#define TWL4030_PM_RECEIVER_REGEN_REMAP			0xDC
+#define TWL4030_PM_RECEIVER_NRESPWRON_DEV_GRP		0xDD
+#define TWL4030_PM_RECEIVER_NRESPWRON_TYPE		0xDE
+#define TWL4030_PM_RECEIVER_NRESPWRON_REMAP		0xDF
+#define TWL4030_PM_RECEIVER_CLKEN_DEV_GRP		0xE0
+#define TWL4030_PM_RECEIVER_CLKEN_TYPE			0xE1
+#define TWL4030_PM_RECEIVER_CLKEN_REMAP			0xE2
+#define TWL4030_PM_RECEIVER_SYSEN_DEV_GRP		0xE3
+#define TWL4030_PM_RECEIVER_SYSEN_TYPE			0xE4
+#define TWL4030_PM_RECEIVER_SYSEN_REMAP			0xE5
+#define TWL4030_PM_RECEIVER_HFCLKOUT_DEV_GRP		0xE6
+#define TWL4030_PM_RECEIVER_HFCLKOUT_TYPE		0xE7
+#define TWL4030_PM_RECEIVER_HFCLKOUT_REMAP		0xE8
+#define TWL4030_PM_RECEIVER_32KCLKOUT_DEV_GRP		0xE9
+#define TWL4030_PM_RECEIVER_32KCLKOUT_TYPE		0xEA
+#define TWL4030_PM_RECEIVER_32KCLKOUT_REMAP		0xEB
+#define TWL4030_PM_RECEIVER_TRITON_RESET_DEV_GRP	0xEC
+#define TWL4030_PM_RECEIVER_TRITON_RESET_TYPE		0xED
+#define TWL4030_PM_RECEIVER_TRITON_RESET_REMAP		0xEE
+#define TWL4030_PM_RECEIVER_MAINREF_DEV_GRP		0xEF
+#define TWL4030_PM_RECEIVER_MAINREF_TYPE		0xF0
+#define TWL4030_PM_RECEIVER_MAINREF_REMAP		0xF1
+
+/* LED */
+#define TWL4030_LED_LEDEN				0xEE
+
+/* Keypad */
+#define TWL4030_KEYPAD_KEYP_CTRL_REG			0xD2
+#define TWL4030_KEYPAD_KEY_DEB_REG			0xD3
+#define TWL4030_KEYPAD_LONG_KEY_REG1			0xD4
+#define TWL4030_KEYPAD_LK_PTV_REG			0xD5
+#define TWL4030_KEYPAD_TIME_OUT_REG1			0xD6
+#define TWL4030_KEYPAD_TIME_OUT_REG2			0xD7
+#define TWL4030_KEYPAD_KBC_REG				0xD8
+#define TWL4030_KEYPAD_KBR_REG				0xD9
+#define TWL4030_KEYPAD_KEYP_SMS				0xDA
+#define TWL4030_KEYPAD_FULL_CODE_7_0			0xDB
+#define TWL4030_KEYPAD_FULL_CODE_15_8			0xDC
+#define TWL4030_KEYPAD_FULL_CODE_23_16			0xDD
+#define TWL4030_KEYPAD_FULL_CODE_31_24			0xDE
+#define TWL4030_KEYPAD_FULL_CODE_39_32			0xDF
+#define TWL4030_KEYPAD_FULL_CODE_47_40			0xE0
+#define TWL4030_KEYPAD_FULL_CODE_55_48			0xE1
+#define TWL4030_KEYPAD_FULL_CODE_63_56			0xE2
+#define TWL4030_KEYPAD_KEYP_ISR1			0xE3
+#define TWL4030_KEYPAD_KEYP_IMR1			0xE4
+#define TWL4030_KEYPAD_KEYP_ISR2			0xE5
+#define TWL4030_KEYPAD_KEYP_IMR2			0xE6
+#define TWL4030_KEYPAD_KEYP_SIR				0xE7
+#define TWL4030_KEYPAD_KEYP_EDR				0xE8
+#define TWL4030_KEYPAD_KEYP_SIH_CTRL			0xE9
+
+#define TWL4030_KEYPAD_CTRL_KBD_ON			(1 << 6)
+#define TWL4030_KEYPAD_CTRL_RP_EN			(1 << 5)
+#define TWL4030_KEYPAD_CTRL_TOLE_EN			(1 << 4)
+#define TWL4030_KEYPAD_CTRL_TOE_EN			(1 << 3)
+#define TWL4030_KEYPAD_CTRL_LK_EN			(1 << 2)
+#define TWL4030_KEYPAD_CTRL_SOFTMODEN			(1 << 1)
+#define TWL4030_KEYPAD_CTRL_SOFT_NRST			(1 << 0)
+
+/* USB */
+#define TWL4030_USB_FUNC_CTRL				(0x04)
+#define TWL4030_USB_OPMODE_MASK				(3 << 3)
+#define TWL4030_USB_XCVRSELECT_MASK			(3 << 0)
+#define TWL4030_USB_IFC_CTRL				(0x07)
+#define TWL4030_USB_CARKITMODE				(1 << 2)
+#define TWL4030_USB_POWER_CTRL				(0xAC)
+#define TWL4030_USB_OTG_ENAB				(1 << 5)
+#define TWL4030_USB_PHY_PWR_CTRL			(0xFD)
+#define TWL4030_USB_PHYPWD				(1 << 0)
+#define TWL4030_USB_PHY_CLK_CTRL			(0xFE)
+#define TWL4030_USB_CLOCKGATING_EN			(1 << 2)
+#define TWL4030_USB_CLK32K_EN				(1 << 1)
+#define TWL4030_USB_REQ_PHY_DPLL_CLK			(1 << 0)
+#define TWL4030_USB_PHY_CLK_CTRL_STS			(0xFF)
+#define TWL4030_USB_PHY_DPLL_CLK			(1 << 0)
+
+/*
+ * Convience functions to read and write from TWL4030
+ *
+ * chip_no is the i2c address, it must be one of the chip addresses
+ *   defined at the top of this file with the prefix TWL4030_CHIP_
+ *   examples are TWL4030_CHIP_PM_RECEIVER and TWL4030_CHIP_KEYPAD
+ *
+ * val is the data either written to or read from the twl4030
+ *
+ * reg is the register to act on, it must be one of the defines
+ *   above and with the format TWL4030_<chip suffix>_<register name>
+ *   examples are TWL4030_PM_RECEIVER_VMMC1_DEV_GRP and
+ *   TWL4030_LED_LEDEN.
+ */
+static inline int twl4030_i2c_write_u8(u8 chip_no, u8 val, u8 reg)
+{
+	return i2c_write(chip_no, reg, 1, &val, 1);
+}
+
+static inline int twl4030_i2c_read_u8(u8 chip_no, u8 *val, u8 reg)
+{
+	return i2c_read(chip_no, reg, 1, val, 1);
+}
+
+/*
+ * Power
+ */
+
+/* For hardware resetting */
+void twl4030_power_reset_init(void);
+/* For initializing power device */
+void twl4030_power_init(void);
+/* For initializing mmc power */
+void twl4030_power_mmc_init(void);
+
+/*
+ * LED
+ */
+void twl4030_led_init(void);
+
+#endif /* TWL4030_H */