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authorAlbert ARIBAUD <albert.u.boot@aribaud.net>2014-05-09 10:47:05 +0200
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2014-05-09 11:50:14 +0200
commitd2a3e911390f9fc4d8c0ee4b3c7fc75f4fd3fd19 (patch)
treed71aae6d706d1f3b01da5f944e247abe308feea0 /include/usb/ehci-fsl.h
parent7904b70885f3c589c239f6ac978f299a6744557f (diff)
parent173d294b94cfec10063a5be40934d6d8fb7981ce (diff)
downloadtalos-obmc-uboot-d2a3e911390f9fc4d8c0ee4b3c7fc75f4fd3fd19.tar.gz
talos-obmc-uboot-d2a3e911390f9fc4d8c0ee4b3c7fc75f4fd3fd19.zip
Merge branch 'u-boot/master'
Conflicts: drivers/net/Makefile (trivial merge)
Diffstat (limited to 'include/usb/ehci-fsl.h')
-rw-r--r--include/usb/ehci-fsl.h7
1 files changed, 7 insertions, 0 deletions
diff --git a/include/usb/ehci-fsl.h b/include/usb/ehci-fsl.h
index 734305b9db..c9ee1d5bf6 100644
--- a/include/usb/ehci-fsl.h
+++ b/include/usb/ehci-fsl.h
@@ -164,6 +164,13 @@
#endif
/*
+ * Increasing TX FIFO threshold value from 2 to 4 decreases
+ * data burst rate with which data packets are posted from the TX
+ * latency FIFO to compensate for latencies in DDR pipeline during DMA
+ */
+#define TXFIFOTHRESH 4
+
+/*
* USB Registers
*/
struct usb_ehci {
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