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| author | Stefan Roese <sr@denx.de> | 2009-10-19 14:06:23 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2009-10-23 16:04:36 +0200 |
| commit | 5e47f9535f53fd4cc05f32fb6166870f976fbb4e (patch) | |
| tree | 68b7e4f2a7167fac1d056de8bcf0b9d5fb4769eb /include/ppc4xx.h | |
| parent | 92b8964bed0d1b779d9e26be4e16755b5c635415 (diff) | |
| download | talos-obmc-uboot-5e47f9535f53fd4cc05f32fb6166870f976fbb4e.tar.gz talos-obmc-uboot-5e47f9535f53fd4cc05f32fb6166870f976fbb4e.zip | |
ppc4xx: Add function to check and dynamically change PCI sync clock
PPC440EP(x)/PPC440GR(x):
In asynchronous PCI mode, the synchronous PCI clock must meet
certain requirements. The following equation describes the
relationship that must be maintained between the asynchronous PCI
clock and synchronous PCI clock. Select an appropriate PCI:PLB
ratio to maintain the relationship:
AsyncPCIClk - 1MHz <= SyncPCIclock <= (2 * AsyncPCIClk) - 1MHz
This patch now adds a function to check and reconfigure the sync
PCI clock to meet this requirement. This is in preparation for
some AMCC boards (Sequoia/Rainier and Yosemite/Yellowstone) using this
function to not violate the PCI clocking rules.
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'include/ppc4xx.h')
| -rw-r--r-- | include/ppc4xx.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/ppc4xx.h b/include/ppc4xx.h index 3bff00a559..5024db447f 100644 --- a/include/ppc4xx.h +++ b/include/ppc4xx.h @@ -221,6 +221,8 @@ static inline void set_mcsr(u32 val) asm volatile("mtspr 0x23c, %0" : "=r" (val) :); } +int ppc4xx_pci_sync_clock_config(u32 async); + #endif /* __ASSEMBLY__ */ /* for multi-cpu support */ |
