diff options
| author | Wolfgang Denk <wd@denx.de> | 2008-01-08 13:41:42 +0100 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2008-01-08 13:41:42 +0100 |
| commit | 207f83f102b07cb186a2da0678c51ed954f1b431 (patch) | |
| tree | 7a225a6e0d30cc5231a5a13aa6bd70ab505e9af7 /include/ppc440.h | |
| parent | 8b0c5c127690335758100c25eaec2b84db97c101 (diff) | |
| parent | e05329516a13616b53240cd85b739217c2bf87f1 (diff) | |
| download | talos-obmc-uboot-207f83f102b07cb186a2da0678c51ed954f1b431.tar.gz talos-obmc-uboot-207f83f102b07cb186a2da0678c51ed954f1b431.zip | |
Merge branch 'master' of git://www.denx.de/git/u-boot-ppc4xx
Diffstat (limited to 'include/ppc440.h')
| -rw-r--r-- | include/ppc440.h | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/include/ppc440.h b/include/ppc440.h index 90e56b0989..bfd1e10338 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -492,6 +492,7 @@ #define SDRAM_ECCCR 0x98 /* ECC error status */ #define SDRAM_CID 0xA4 /* core ID */ #define SDRAM_RID 0xA8 /* revision ID */ +#define SDRAM_RTSR 0xB1 /* run time status tracking */ /*-----------------------------------------------------------------------------+ | Memory Controller Status @@ -605,8 +606,8 @@ #define SDRAM_RFDC_ARSE_ENABLE 0x00000000 #define SDRAM_RFDC_RFOS_MASK 0x007F0000 #define SDRAM_RFDC_RFOS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16) -#define SDRAM_RFDC_RFFD_MASK 0x000003FF -#define SDRAM_RFDC_RFFD_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0) +#define SDRAM_RFDC_RFFD_MASK 0x000007FF +#define SDRAM_RFDC_RFFD_ENCODE(n) ((((unsigned long)(n))&0x7FF)<<0) #define SDRAM_RFDC_RFFD_MAX 0x7FF @@ -690,6 +691,7 @@ #define SDRAM_CLKTR_CLKP_MASK 0xC0000000 #define SDRAM_CLKTR_CLKP_0_DEG 0x00000000 #define SDRAM_CLKTR_CLKP_180_DEG_ADV 0x80000000 +#define SDRAM_CLKTR_CLKP_90_DEG_ADV 0x40000000 /*-----------------------------------------------------------------------------+ | SDRAM Write Timing Register @@ -790,6 +792,12 @@ #define SDRAM_BXCF_M_BE_DISABLE 0x00000000 /* Memory Bank Enable */ #define SDRAM_BXCF_M_BE_ENABLE 0x00000001 /* Memory Bank Enable */ +#define SDRAM_RTSR_TRK1SM_MASK 0xC0000000 /* Tracking State Mach 1*/ +#define SDRAM_RTSR_TRK1SM_ATBASE 0x00000000 /* atbase state */ +#define SDRAM_RTSR_TRK1SM_MISSED 0x40000000 /* missed state */ +#define SDRAM_RTSR_TRK1SM_ATPLS1 0x80000000 /* atpls1 state */ +#define SDRAM_RTSR_TRK1SM_RESET 0xC0000000 /* reset state */ + #define SDR0_MFR_FIXD 0x10000000 /* Workaround for PCI/DMA */ #endif /* CONFIG_440SPE */ |
