diff options
| author | Michael Barkowski <michael.barkowski@freescale.com> | 2008-03-20 13:15:34 -0400 |
|---|---|---|
| committer | Kim Phillips <kim.phillips@freescale.com> | 2008-03-25 19:16:44 -0500 |
| commit | 5bbeea86eb6afb872374cd23217cb3c1018443ed (patch) | |
| tree | 788ab3805bc7a7198f9a106e9752e3c550449901 /include/mpc83xx.h | |
| parent | fc549c871f43933396a5b3e21d897023d4b31b8d (diff) | |
| download | talos-obmc-uboot-5bbeea86eb6afb872374cd23217cb3c1018443ed.tar.gz talos-obmc-uboot-5bbeea86eb6afb872374cd23217cb3c1018443ed.zip | |
mpc8323erdb: Improve the system performance
The following changes are based on kernel UCC ethernet performance:
1. Make the CSB bus pipeline depth as 4, and enable the repeat mode
2. Optimize transactions between QE and CSB. Added CFG_SPCR_OPT
switch to enable this setting.
The following changes are based on the App Note AN3369 and
verified to improve memory latency using LMbench:
3. CS0_CONFIG[AP_n_EN] is changed from 1 to 0
4. CS0_CONFIG[ODT_WR_CONFIG] set to 1. Was a reserved setting
previously.
5. TIMING_CFG_1[WRREC] is changed from 3clks to 2clks (based on
Twr=15ns, and this was already the setting in DDR_MODE)
6. TIMING_CFG_1[PRETOACT] is changed from 3clks to 2clks. (based on
Trp=15ns)
7. TIMING_CFG_1[ACTTOPRE] is changed from 9clks to 6clks. (based on
Tras=40ns)
8. TIMING_CFG_1[ACTTORW] is changed from 3clks to 2clks. (based on
Trcd=15ns)
9. TIMING_CFG_1[REFREC] changed from 21 clks to 11clks. (based on
Trfc=75ns)
10. TIMING_CFG_2[FOUR_ACT] is changed from 10 clks to 7clks. (based
on Tfaw=50ns)
11. TIMING_CFG_2[ADD_LAT] and DDR_MODE[AL] changed from 0 to 1 (based
on CL=3 and WL=2).
Signed-off-by: Michael Barkowski <michael.barkowski@freescale.com>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Diffstat (limited to 'include/mpc83xx.h')
| -rw-r--r-- | include/mpc83xx.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/mpc83xx.h b/include/mpc83xx.h index df052e3d4c..e84442b7ba 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -121,6 +121,7 @@ #define SPCR_PCIPR 0x03000000 /* PCI bridge system bus request priority */ #define SPCR_PCIPR_SHIFT (31-7) #define SPCR_OPT 0x00800000 /* Optimize */ +#define SPCR_OPT_SHIFT (31-8) #define SPCR_TBEN 0x00400000 /* E300 PowerPC core time base unit enable */ #define SPCR_TBEN_SHIFT (31-9) #define SPCR_COREPR 0x00300000 /* E300 PowerPC Core system bus request priority */ |
