Merge branch 'topic/arm/socfpga-20141006' of git://git.denx.de/u-boot-socfpga

Fix a trivial conflict in dw_mmc.c after talking with Marek.

Conflicts:
	drivers/mmc/dw_mmc.c

Signed-off-by: Tom Rini <trini@ti.com>

3 files changed, 261 insertions, 253 deletions

diff --git a/include/configs/axs101.h b/include/configs/axs101.h
index c22d6d0c75..1bf8390722 100644
--- a/include/configs/axs101.h
+++ b/include/configs/axs101.h
@@ -125,7 +125,6 @@
  */
 #define CONFIG_DESIGNWARE_ETH
 #define CONFIG_DW_AUTONEG
-#define CONFIG_DW_SEARCH_PHY
 #define CONFIG_NET_MULTI
 
 /*
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
new file mode 100644
index 0000000000..49504dcafb
--- /dev/null
+++ b/include/configs/socfpga_common.h
@@ -0,0 +1,196 @@
+/*
+ * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__
+#define __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__
+
+#define CONFIG_SYS_GENERIC_BOARD
+
+/* Virtual target or real hardware */
+#undef CONFIG_SOCFPGA_VIRTUAL_TARGET
+
+#define CONFIG_ARMV7
+#define CONFIG_SYS_THUMB_BUILD
+
+#define CONFIG_SOCFPGA
+
+/*
+ * High level configuration
+ */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_MISC_INIT_R
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_CLOCKS
+
+#define CONFIG_FIT
+#define CONFIG_OF_LIBFDT
+#define CONFIG_SYS_BOOTMAPSZ		(64 * 1024 * 1024)
+
+#define CONFIG_TIMESTAMP		/* Print image info with timestamp */
+
+/*
+ * Memory configurations
+ */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM_1			0x0
+#define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)
+#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_1
+#define CONFIG_SYS_MEMTEST_END		PHYS_SDRAM_1_SIZE
+
+#define CONFIG_SYS_INIT_RAM_ADDR	0xFFFF0000
+#define CONFIG_SYS_INIT_RAM_SIZE	(0x10000 - 0x100)
+#define CONFIG_SYS_INIT_SP_ADDR					\
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE -	\
+	GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
+#define CONFIG_SYS_TEXT_BASE		0x08000040
+#else
+#define CONFIG_SYS_TEXT_BASE		0x01000040
+#endif
+
+/*
+ * U-Boot general configurations
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O buffer size */
+#define CONFIG_SYS_PBSIZE	\
+	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+						/* Print buffer size */
+#define CONFIG_SYS_MAXARGS	32		/* Max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+						/* Boot argument buffer size */
+#define CONFIG_VERSION_VARIABLE			/* U-BOOT version */
+#define CONFIG_AUTO_COMPLETE			/* Command auto complete */
+#define CONFIG_CMDLINE_EDITING			/* Command history etc */
+#define CONFIG_SYS_HUSH_PARSER
+
+/*
+ * Cache
+ */
+#define CONFIG_SYS_ARM_CACHE_WRITEALLOC
+#define CONFIG_SYS_CACHELINE_SIZE 32
+#define CONFIG_SYS_L2_PL310
+#define CONFIG_SYS_PL310_BASE		SOCFPGA_MPUL2_ADDRESS
+
+/*
+ * Ethernet on SoC (EMAC)
+ */
+#if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
+#define CONFIG_DESIGNWARE_ETH
+#define CONFIG_NET_MULTI
+#define CONFIG_DW_ALTDESCRIPTOR
+#define CONFIG_MII
+#define CONFIG_AUTONEG_TIMEOUT		(15 * CONFIG_SYS_HZ)
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_GIGE
+#endif
+
+/*
+ * FPGA Driver
+ */
+#ifdef CONFIG_CMD_FPGA
+#define CONFIG_FPGA
+#define CONFIG_FPGA_ALTERA
+#define CONFIG_FPGA_SOCFPGA
+#define CONFIG_FPGA_COUNT		1
+#endif
+
+/*
+ * L4 OSC1 Timer 0
+ */
+/* This timer uses eosc1, whose clock frequency is fixed at any condition. */
+#define CONFIG_SYS_TIMERBASE		SOCFPGA_OSC1TIMER0_ADDRESS
+#define CONFIG_SYS_TIMER_COUNTS_DOWN
+#define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMERBASE + 0x4)
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
+#define CONFIG_SYS_TIMER_RATE		2400000
+#else
+#define CONFIG_SYS_TIMER_RATE		25000000
+#endif
+
+/*
+ * L4 Watchdog
+ */
+#ifdef CONFIG_HW_WATCHDOG
+#define CONFIG_DESIGNWARE_WATCHDOG
+#define CONFIG_DW_WDT_BASE		SOCFPGA_L4WD0_ADDRESS
+#define CONFIG_DW_WDT_CLOCK_KHZ		25000
+#define CONFIG_HW_WATCHDOG_TIMEOUT_MS	12000
+#endif
+
+/*
+ * MMC Driver
+ */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_BOUNCE_BUFFER
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DWMMC
+#define CONFIG_SOCFPGA_DWMMC
+#define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH	1024
+#define CONFIG_SOCFPGA_DWMMC_DRVSEL	3
+#define CONFIG_SOCFPGA_DWMMC_SMPSEL	0
+/* FIXME */
+/* using smaller max blk cnt to avoid flooding the limited stack we have */
+#define CONFIG_SYS_MMC_MAX_BLK_COUNT	256	/* FIXME -- SPL only? */
+#endif
+
+/*
+ * Serial Driver
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	-4
+#define CONFIG_SYS_NS16550_COM1		SOCFPGA_UART0_ADDRESS
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
+#define CONFIG_SYS_NS16550_CLK		1000000
+#else
+#define CONFIG_SYS_NS16550_CLK		100000000
+#endif
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_BAUDRATE			115200
+
+/*
+ * U-Boot environment
+ */
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE			4096
+
+/*
+ * SPL
+ */
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_RAM_DEVICE
+#define CONFIG_SPL_TEXT_BASE		0xFFFF0000
+#define CONFIG_SPL_STACK		CONFIG_SYS_INIT_SP_ADDR
+#define CONFIG_SPL_STACK_SIZE		(4 * 1024)
+#define CONFIG_SPL_MALLOC_SIZE		(5 * 1024)	/* FIXME */
+#define CONFIG_SYS_SPL_MALLOC_START	((unsigned long) (&__malloc_start))
+#define CONFIG_SYS_SPL_MALLOC_SIZE	(&__malloc_end - &__malloc_start)
+
+#define CHUNKSZ_CRC32			(1 * 1024)	/* FIXME: ewww */
+#define CONFIG_CRC32_VERIFY
+
+/* Linker script for SPL */
+#define CONFIG_SPL_LDSCRIPT	"arch/arm/cpu/armv7/socfpga/u-boot-spl.lds"
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_WATCHDOG_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+
+#ifdef CONFIG_SPL_BUILD
+#undef CONFIG_PARTITIONS
+#endif
+
+#endif	/* __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ */
diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h
index 5d145cd821..8d54bf892d 100644
--- a/include/configs/socfpga_cyclone5.h
+++ b/include/configs/socfpga_cyclone5.h
@@ -1,287 +1,100 @@
 /*
- *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ * Copyright (C) 2014 Marek Vasut <marex@denx.de>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
-#ifndef __CONFIG_H
-#define __CONFIG_H
+#ifndef __CONFIG_SOCFPGA_CYCLONE5_H__
+#define __CONFIG_SOCFPGA_CYCLONE5_H__
 
 #include <asm/arch/socfpga_base_addrs.h>
 #include "../../board/altera/socfpga/pinmux_config.h"
 #include "../../board/altera/socfpga/iocsr_config.h"
 #include "../../board/altera/socfpga/pll_config.h"
 
-/*
- * High level configuration
- */
-/* Virtual target or real hardware */
-#undef CONFIG_SOCFPGA_VIRTUAL_TARGET
-
-#define CONFIG_ARMV7
-#define CONFIG_SYS_DCACHE_OFF
-#undef CONFIG_USE_IRQ
-
-#define CONFIG_MISC_INIT_R
-#define CONFIG_SINGLE_BOOTLOADER
-#define CONFIG_SOCFPGA
-
-/* base address for .text section */
-#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
-#define CONFIG_SYS_TEXT_BASE		0x08000040
-#else
-#define CONFIG_SYS_TEXT_BASE		0x01000040
-#endif
-#define CONFIG_SYS_LOAD_ADDR		0x7fc0
-
-/* Console I/O Buffer Size */
-#define CONFIG_SYS_CBSIZE		256
-/* Monitor Command Prompt */
-#define CONFIG_SYS_PROMPT		"SOCFPGA_CYCLONE5 # "
-#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
-					sizeof(CONFIG_SYS_PROMPT) + 16)
-
-/*
- * Display CPU and Board Info
- */
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
-/*
- * Enable early stage initialization at C environment
- */
-#define CONFIG_BOARD_EARLY_INIT_F
-
-/* flat device tree */
-#define CONFIG_OF_LIBFDT
-/* skip updating the FDT blob */
-#define CONFIG_FDT_BLOB_SKIP_UPDATE
-/* Initial Memory map size for Linux, minus 4k alignment for DFT blob */
-#define CONFIG_SYS_BOOTMAPSZ		((256*1024*1024) - (4*1024))
-
-#define CONFIG_SPL_RAM_DEVICE
-#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
-#define CONFIG_SYS_SPL_MALLOC_START ((unsigned long) (&__malloc_start))
-#define CONFIG_SYS_SPL_MALLOC_SIZE (&__malloc_end - &__malloc_start)
-
-/*
- * Memory allocation (MALLOC)
- */
-/* Room required on the stack for the environment data */
-#define CONFIG_ENV_SIZE			1024
-/* Size of DRAM reserved for malloc() use */
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
-
-/* SP location before relocation, must use scratch RAM */
-#define CONFIG_SYS_INIT_RAM_ADDR	0xFFFF0000
-/* Reserving 0x100 space at back of scratch RAM for debug info */
-#define CONFIG_SYS_INIT_RAM_SIZE	(0x10000 - 0x100)
-/* Stack pointer prior relocation, must situated at on-chip RAM */
-#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_SIZE - \
-					 GENERATED_GBL_DATA_SIZE)
-
-
-/*
- * Command line configuration.
- */
+/* U-Boot Commands */
 #define CONFIG_SYS_NO_FLASH
 #include <config_cmd_default.h>
-/* FAT file system support */
+#define CONFIG_DOS_PARTITION
+#define CONFIG_FAT_WRITE
+#define CONFIG_HW_WATCHDOG
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
 #define CONFIG_CMD_FAT
+#define CONFIG_CMD_FPGA
+#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SETEXPR
 
+#define CONFIG_REGEX			/* Enable regular expression support */
 
-/*
- * Misc
- */
-#define CONFIG_DOS_PARTITION            1
+/* Memory configurations */
+#define PHYS_SDRAM_1_SIZE		0x40000000	/* 1GiB on SoCDK */
 
-#ifdef CONFIG_SPL_BUILD
-#undef CONFIG_PARTITIONS
+/* Booting Linux */
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTFILE		"zImage"
+#define CONFIG_BOOTARGS		"console=ttyS0" __stringify(CONFIG_BAUDRATE)
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
+#define CONFIG_BOOTCOMMAND	"run ramboot"
+#else
+#define CONFIG_BOOTCOMMAND	"run mmcload; run mmcboot"
 #endif
+#define CONFIG_LOADADDR		0x8000
+#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
 
-/*
- * Environment setup
- */
+/* Ethernet on SoC (EMAC) */
+#if defined(CONFIG_CMD_NET)
+#define CONFIG_EMAC_BASE		SOCFPGA_EMAC0_ADDRESS
+#define CONFIG_PHY_INTERFACE_MODE	PHY_INTERFACE_MODE_RGMII
+#define CONFIG_EPHY0_PHY_ADDR		0
 
-/* Delay before automatically booting the default image */
-#define CONFIG_BOOTDELAY		3
-/* Enable auto completion of commands using TAB */
-#define CONFIG_AUTO_COMPLETE
-/* use "hush" command parser */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
-#define CONFIG_CMD_RUN
+/* PHY */
+#define CONFIG_EPHY1_PHY_ADDR		4
+#define CONFIG_PHY_MICREL
+#define CONFIG_PHY_MICREL_KSZ9021
+#define CONFIG_KSZ9021_CLK_SKEW_ENV	"micrel-ksz9021-clk-skew"
+#define CONFIG_KSZ9021_CLK_SKEW_VAL	0xf0f0
+#define CONFIG_KSZ9021_DATA_SKEW_ENV	"micrel-ksz9021-data-skew"
+#define CONFIG_KSZ9021_DATA_SKEW_VAL	0x0
 
-#define CONFIG_BOOTCOMMAND "run ramboot"
+#endif
 
-/*
- * arguments passed to the bootm command. The value of
- * CONFIG_BOOTARGS goes into the environment value "bootargs".
- * Do note the value will overide also the chosen node in FDT blob.
- */
-#define CONFIG_BOOTARGS "console=ttyS0,57600,mem=256M@0x0"
+/* Extra Environment */
+#define CONFIG_HOSTNAME		socfpga_cyclone5
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"verify=n\0" \
 	"loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
 	"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
 		"bootm ${loadaddr} - ${fdt_addr}\0" \
-	"bootimage=uImage\0" \
+	"bootimage=zImage\0" \
 	"fdt_addr=100\0" \
-	"fsloadcmd=ext2load\0" \
-		"bootm ${loadaddr} - ${fdt_addr}\0" \
+	"fdtimage=socfpga.dtb\0" \
+		"fsloadcmd=ext2load\0" \
+	"bootm ${loadaddr} - ${fdt_addr}\0" \
+	"mmcroot=/dev/mmcblk0p2\0" \
+	"mmcboot=setenv bootargs " CONFIG_BOOTARGS \
+		" root=${mmcroot} rw rootwait;" \
+		"bootz ${loadaddr} - ${fdt_addr}\0" \
+	"mmcload=mmc rescan;" \
+		"load mmc 0:1 ${loadaddr} ${bootimage};" \
+		"load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
 	"qspiroot=/dev/mtdblock0\0" \
 	"qspirootfstype=jffs2\0" \
 	"qspiboot=setenv bootargs " CONFIG_BOOTARGS \
 		" root=${qspiroot} rw rootfstype=${qspirootfstype};"\
 		"bootm ${loadaddr} - ${fdt_addr}\0"
 
-/* using environment setting for stdin, stdout, stderr */
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-/* Enable the call to overwrite_console() */
-#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
-/* Enable overwrite of previous console environment settings */
-#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
-
-/* max number of command args	 */
-#define CONFIG_SYS_MAXARGS		16
-
-
-/*
- * Hardware drivers
- */
-
-/*
- * SDRAM Memory Map
- */
-/* We have 1 bank of DRAM */
-#define CONFIG_NR_DRAM_BANKS		1
-/* SDRAM Bank #1 */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-/* SDRAM memory size */
-#define PHYS_SDRAM_1_SIZE		0x40000000
-
-#define PHYS_SDRAM_1			CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_START	0x00000000
-#define CONFIG_SYS_MEMTEST_END		PHYS_SDRAM_1_SIZE
-
-/*
- * NS16550 Configuration
- */
-#define UART0_BASE			SOCFPGA_UART0_ADDRESS
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	-4
-#define CONFIG_SYS_NS16550_CLK          V_NS16550_CLK
-#define CONFIG_CONS_INDEX               1
-#define CONFIG_SYS_NS16550_COM1		UART0_BASE
-#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
-#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
-#define V_NS16550_CLK			1000000
-#else
-#define V_NS16550_CLK			100000000
-#endif
-#define CONFIG_BAUDRATE			115200
-
-/*
- * FLASH
- */
-#define CONFIG_SYS_NO_FLASH
-
-/*
- * L4 OSC1 Timer 0
- */
-/* This timer use eosc1 where the clock frequency is fixed
- * throughout any condition */
-#define CONFIG_SYS_TIMERBASE		SOCFPGA_OSC1TIMER0_ADDRESS
-/* reload value when timer count to zero */
-#define TIMER_LOAD_VAL			0xFFFFFFFF
-/* Timer info */
-#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
-#define CONFIG_SYS_TIMER_RATE		2400000
-#else
-#define CONFIG_SYS_TIMER_RATE		25000000
-#endif
-#define CONFIG_SYS_TIMER_COUNTS_DOWN
-#define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMERBASE + 0x4)
-
-#define CONFIG_ENV_IS_NOWHERE
-
-/*
- * network support
- */
-#ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
-#define CONFIG_DESIGNWARE_ETH          1
-#endif
-
-#ifdef CONFIG_DESIGNWARE_ETH
-#define CONFIG_EMAC0_BASE              SOCFPGA_EMAC0_ADDRESS
-#define CONFIG_EMAC1_BASE              SOCFPGA_EMAC1_ADDRESS
-/* console support for network */
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_PING
-/* designware */
-#define CONFIG_NET_MULTI
-#define CONFIG_DW_ALTDESCRIPTOR
-#define CONFIG_DW_SEARCH_PHY
-#define CONFIG_MII
-#define CONFIG_PHY_GIGE
-#define CONFIG_DW_AUTONEG
-#define CONFIG_AUTONEG_TIMEOUT         (15 * CONFIG_SYS_HZ)
-#define CONFIG_PHYLIB
-#define CONFIG_PHY_MICREL
-#define CONFIG_PHY_MICREL_KSZ9021
-/* EMAC controller and PHY used */
-#define CONFIG_EMAC_BASE               CONFIG_EMAC1_BASE
-#define CONFIG_EPHY_PHY_ADDR           CONFIG_EPHY1_PHY_ADDR
-#define CONFIG_PHY_INTERFACE_MODE      PHY_INTERFACE_MODE_RGMII
-#endif /* CONFIG_DESIGNWARE_ETH */
-
-/*
- * L4 Watchdog
- */
-#define CONFIG_HW_WATCHDOG
-#define CONFIG_HW_WATCHDOG_TIMEOUT_MS	2000
-#define CONFIG_DESIGNWARE_WATCHDOG
-#define CONFIG_DW_WDT_BASE		SOCFPGA_L4WD0_ADDRESS
-/* Clocks source frequency to watchdog timer */
-#define CONFIG_DW_WDT_CLOCK_KHZ		25000
-
-
-/*
- * SPL "Second Program Loader" aka Initial Software
- */
-
-/* Enable building of SPL globally */
-#define CONFIG_SPL_FRAMEWORK
-
-/* TEXT_BASE for linking the SPL binary */
-#define CONFIG_SPL_TEXT_BASE		0xFFFF0000
-
-/* Stack size for SPL */
-#define CONFIG_SPL_STACK_SIZE		(4 * 1024)
-
-/* MALLOC size for SPL */
-#define CONFIG_SPL_MALLOC_SIZE		(5 * 1024)
-
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_BOARD_INIT
-
-#define CHUNKSZ_CRC32			(1 * 1024)
-
-#define CONFIG_CRC32_VERIFY
-
-/* Linker script for SPL */
-#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/socfpga/u-boot-spl.lds"
-
-/* Support for common/libcommon.o in SPL binary */
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-/* Support for lib/libgeneric.o in SPL binary */
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-
-/* Support for watchdog */
-#define CONFIG_SPL_WATCHDOG_SUPPORT
+/* The rest of the configuration is shared */
+#include <configs/socfpga_common.h>
 
-#endif	/* __CONFIG_H */
+#endif	/* __CONFIG_SOCFPGA_CYCLONE5_H__ */