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| author | Alexander Graf <agraf@suse.de> | 2016-03-04 01:09:47 +0100 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2016-03-15 15:13:01 -0400 |
| commit | 5e2ec773bb6c5acf22d8652112856e87cff86ea4 (patch) | |
| tree | ae75a1cab47d1d59c91ccc5a5d2579c64dab47a1 /include/configs/thunderx_88xx.h | |
| parent | 9bb367a590feac21d674e4d2cee77702d4774819 (diff) | |
| download | talos-obmc-uboot-5e2ec773bb6c5acf22d8652112856e87cff86ea4.tar.gz talos-obmc-uboot-5e2ec773bb6c5acf22d8652112856e87cff86ea4.zip | |
arm64: Make full va map code more dynamic
The idea to generate our pages tables from an array of memory ranges
is very sound. However, instead of hard coding the code to create up
to 2 levels of 64k granule page tables, we really should just create
normal 4k page tables that allow us to set caching attributes on 2M
or 4k level later on.
So this patch moves the full_va mapping code to 4k page size and
makes it fully flexible to dynamically create as many levels as
necessary for a map (including dynamic 1G/2M pages). It also adds
support to dynamically split a large map into smaller ones when
some code wants to set dcache attributes.
With all this in place, there is very little reason to create your
own page tables in board specific files.
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'include/configs/thunderx_88xx.h')
| -rw-r--r-- | include/configs/thunderx_88xx.h | 14 |
1 files changed, 6 insertions, 8 deletions
diff --git a/include/configs/thunderx_88xx.h b/include/configs/thunderx_88xx.h index dba98ad422..36b6ce8df2 100644 --- a/include/configs/thunderx_88xx.h +++ b/include/configs/thunderx_88xx.h @@ -22,21 +22,19 @@ #define MEM_BASE 0x00500000 -#define CONFIG_COREID_MASK 0xffffff - #define CONFIG_SYS_FULL_VA #define CONFIG_SYS_LOWMEM_BASE MEM_BASE #define CONFIG_SYS_MEM_MAP {{0x000000000000UL, 0x40000000000UL, \ - PTL2_MEMTYPE(MT_NORMAL) | \ - PTL2_BLOCK_NON_SHARE}, \ + PTE_BLOCK_MEMTYPE(MT_NORMAL) | \ + PTE_BLOCK_NON_SHARE}, \ {0x800000000000UL, 0x40000000000UL, \ - PTL2_MEMTYPE(MT_DEVICE_NGNRNE) | \ - PTL2_BLOCK_NON_SHARE}, \ + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | \ + PTE_BLOCK_NON_SHARE}, \ {0x840000000000UL, 0x40000000000UL, \ - PTL2_MEMTYPE(MT_DEVICE_NGNRNE) | \ - PTL2_BLOCK_NON_SHARE}, \ + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | \ + PTE_BLOCK_NON_SHARE}, \ } #define CONFIG_SYS_MEM_MAP_SIZE 3 |
