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| author | Paul Gortmaker <paul.gortmaker@windriver.com> | 2011-12-30 23:53:07 -0500 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2012-01-11 13:58:10 -0600 |
| commit | 3fd673cf363bc86ed42eff713d4e3506720e91a2 (patch) | |
| tree | 81c598c3b6e11409cf4f9b83d819e857ed95dbfe /include/configs/sbc8548.h | |
| parent | af35be6ac962a737005737ab479da93cac2f596f (diff) | |
| download | talos-obmc-uboot-3fd673cf363bc86ed42eff713d4e3506720e91a2.tar.gz talos-obmc-uboot-3fd673cf363bc86ed42eff713d4e3506720e91a2.zip | |
sbc8548: relocate 64MB user flash to sane boundary
The current situation has the 64MB user flash at an awkward
alignment; shifted back from 0xfc00_0000 by 8M, to leave an 8MB hole
for the soldered on boot flash @ EOM. But to switch to optionally
supporting booting off the 64MB flash, the 64MB will then be mapped
at the sane address of 0xfc00_0000.
This leads to awkward things when programming the 64MB flash prior
to transitioning to it -- i.e. even though the chip spans from
0xfb80_0000 to 0xff7f_ffff, you would have to program a u-boot image
into the two sectors from 0xfbf0_0000 --> 0xfbff_ffff so that it was
in the right place when JP12/SW2.8 were switched to make the 64MB on
/CS0. (i.e. the chip is only looking at the bits in mask 0x3ff_ffff)
We also have to have three TLB entries responsible for dealing with
mapping the 64MB flash due to this 8MB of misalignment.
In the end, there is address space from 0xec00_0000 to 0xefff_ffff
where we can map it, and then the transition from booting from one
config to the other will be a simple 0xec --> 0xfc mapping. Plus we
can toss out a TLB entry.
Note that TLB0 is kept at 64MB and not shrunk down to the 8MB boot
flash; this means we won't have to change it when the alternate
config uses the full 64MB for booting, in TLB0.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'include/configs/sbc8548.h')
| -rw-r--r-- | include/configs/sbc8548.h | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index 7c26207ab9..cea017900f 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -140,7 +140,7 @@ * FLASH on the Local Bus * Two banks, one 8MB the other 64MB, using the CFI driver. * Boot from BR0/OR0 bank at 0xff80_0000 - * Alternate BR6/OR6 bank at 0xfb80_0000 + * Alternate BR6/OR6 bank at 0xec00_0000 * * BR0: * Base address 0 = 0xff80_0000 = BR0[0:16] = 1111 1111 1000 0000 0 @@ -152,13 +152,13 @@ * 1111 1111 1000 0000 0000 1000 0000 0001 = ff800801 BR0 * * BR6: - * Base address 6 = 0xfb80_0000 = BR6[0:16] = 1111 1011 1000 0000 0 + * Base address 6 = 0xec00_0000 = BR6[0:16] = 1110 1100 0000 0000 0 * Port Size = 32 bits = BRx[19:20] = 11 * Use GPCM = BRx[24:26] = 000 * Valid = BRx[31] = 1 * * 0 4 8 12 16 20 24 28 - * 1111 1011 1000 0000 0001 1000 0000 0001 = fb801801 BR6 + * 1110 1100 0000 0000 0001 1000 0000 0001 = ec001801 BR6 * * OR0: * Addr Mask = 8M = OR1[0:16] = 1111 1111 1000 0000 0 @@ -186,11 +186,11 @@ */ #define CONFIG_SYS_BOOT_BLOCK 0xff800000 /* start of 8MB Flash */ -#define CONFIG_SYS_ALT_FLASH 0xfb800000 /* 64MB "user" flash */ +#define CONFIG_SYS_ALT_FLASH 0xec000000 /* 64MB "user" flash */ #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of FLASH 16M */ #define CONFIG_SYS_BR0_PRELIM 0xff800801 -#define CONFIG_SYS_BR6_PRELIM 0xfb801801 +#define CONFIG_SYS_BR6_PRELIM 0xec001801 #define CONFIG_SYS_OR0_PRELIM 0xff806e65 #define CONFIG_SYS_OR6_PRELIM 0xfc006e65 |
