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| author | Tom Rini <trini@ti.com> | 2011-11-18 12:48:09 +0000 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2011-12-06 23:59:38 +0100 |
| commit | 673283f3fc2583a56b3be995cd341159428734ba (patch) | |
| tree | 31c3ec0d2ac75d8c82fe39504d71e6441c413652 /include/configs/omap3_evm_common.h | |
| parent | 75c57a3570ec0904c14394db08ef436a8b49dda4 (diff) | |
| download | talos-obmc-uboot-673283f3fc2583a56b3be995cd341159428734ba.tar.gz talos-obmc-uboot-673283f3fc2583a56b3be995cd341159428734ba.zip | |
OMAP3: Add SPL support to omap3_evm
Add Hynix 200MHz timing information to <asm/arch-omap3/mem.h>.
This also changes CONFIG_SYS_TEXT_BASE to 0x80100000.
Signed-off-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'include/configs/omap3_evm_common.h')
| -rw-r--r-- | include/configs/omap3_evm_common.h | 30 |
1 files changed, 28 insertions, 2 deletions
diff --git a/include/configs/omap3_evm_common.h b/include/configs/omap3_evm_common.h index d62d2abe37..b256317905 100644 --- a/include/configs/omap3_evm_common.h +++ b/include/configs/omap3_evm_common.h @@ -26,7 +26,6 @@ #define CONFIG_SDRC /* The chip has SDRC controller */ #define CONFIG_OMAP3_EVM /* This is a OMAP3 EVM */ -#define CONFIG_OMAP3_MICRON_DDR /* with MICRON DDR part */ #define CONFIG_TWL4030_POWER /* with TWL4030 PMIC */ #undef CONFIG_USE_IRQ /* no support for IRQs */ @@ -65,7 +64,6 @@ */ #define CONFIG_NR_DRAM_BANKS 2 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_1_SIZE (32 << 20) #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 /* Limits for memtest */ @@ -282,4 +280,32 @@ #define CONFIG_SYS_CACHELINE_SIZE 64 +/* Defines for SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_TEXT_BASE 0x40200800 +#define CONFIG_SPL_MAX_SIZE (45 * 1024) /* 45 KB */ +#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK + +#define CONFIG_SPL_BSS_START_ADDR 0x80000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_OMAP3_ID_NAND +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" + +/* + * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM + * 64 bytes before this address should be set aside for u-boot.img's + * header. That is 0x800FFFC0--0x80100000 should not be used for any + * other needs. + */ +#define CONFIG_SYS_TEXT_BASE 0x80100000 +#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 + #endif /* __OMAP3_EVM_COMMON_H */ |
