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| author | Martha M Stan <mmarx@silicontkx.com> | 2009-09-21 14:07:14 -0400 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2009-09-25 00:45:30 +0200 |
| commit | 054197ba8ee5ef1e41694df58531b6e53ec43f2d (patch) | |
| tree | cd9c07cf88ea69f6af85ad8a0ceb42d80b1c7549 /include/configs/mpc5121ads.h | |
| parent | 5e498dfab87c5b9bd1ad7b9a35f38b9e5dcd2244 (diff) | |
| download | talos-obmc-uboot-054197ba8ee5ef1e41694df58531b6e53ec43f2d.tar.gz talos-obmc-uboot-054197ba8ee5ef1e41694df58531b6e53ec43f2d.zip | |
mpc512x: Streamlined fixed_sdram() init sequence.
Signed-off-by: Martha M Stan <mmarx@silicontkx.com>
Minor cleanup:
Re-ordered default_mddrc_config[] to have matching indices.
This allows to use the same index "N" for source and target fields;
before, we had code like this
out_be32(&im->mddrc.ddr_time_config2, mddrc_config[3]);
which always looked like a copy & paste error because 2 != 3.
Also, use NULL when meaning a null pointer.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Diffstat (limited to 'include/configs/mpc5121ads.h')
| -rw-r--r-- | include/configs/mpc5121ads.h | 30 |
1 files changed, 13 insertions, 17 deletions
diff --git a/include/configs/mpc5121ads.h b/include/configs/mpc5121ads.h index 76f174db3f..0c871c9195 100644 --- a/include/configs/mpc5121ads.h +++ b/include/configs/mpc5121ads.h @@ -131,28 +131,24 @@ * [04:00] DRAM tRPA */ #ifdef CONFIG_MPC5121ADS_REV2 -#define CONFIG_SYS_MDDRC_SYS_CFG 0xF8604A00 -#define CONFIG_SYS_MDDRC_SYS_CFG_RUN 0xE8604A00 +#define CONFIG_SYS_MDDRC_SYS_CFG 0xE8604A00 #define CONFIG_SYS_MDDRC_TIME_CFG1 0x54EC1168 #define CONFIG_SYS_MDDRC_TIME_CFG2 0x35210864 #else -#define CONFIG_SYS_MDDRC_SYS_CFG 0xFA804A00 -#define CONFIG_SYS_MDDRC_SYS_CFG_RUN 0xEA804A00 -#define CONFIG_SYS_MDDRC_TIME_CFG1 0x68EC1168 -#define CONFIG_SYS_MDDRC_TIME_CFG2 0x34310864 +#define CONFIG_SYS_MDDRC_SYS_CFG 0xEA804A00 +#define CONFIG_SYS_MDDRC_TIME_CFG1 0x68EC1168 +#define CONFIG_SYS_MDDRC_TIME_CFG2 0x34310864 #endif -#define CONFIG_SYS_MDDRC_SYS_CFG_EN 0xF0000000 -#define CONFIG_SYS_MDDRC_TIME_CFG0 0x00003D2E -#define CONFIG_SYS_MDDRC_TIME_CFG0_RUN 0x06183D2E - -#define CONFIG_SYS_MICRON_NOP 0x01380000 -#define CONFIG_SYS_MICRON_PCHG_ALL 0x01100400 -#define CONFIG_SYS_MICRON_EM2 0x01020000 -#define CONFIG_SYS_MICRON_EM3 0x01030000 -#define CONFIG_SYS_MICRON_EN_DLL 0x01010000 -#define CONFIG_SYS_MICRON_RFSH 0x01080000 +#define CONFIG_SYS_MDDRC_TIME_CFG0 0x06183D2E + +#define CONFIG_SYS_DDRCMD_NOP 0x01380000 +#define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400 +#define CONFIG_SYS_DDRCMD_EM2 0x01020000 +#define CONFIG_SYS_DDRCMD_EM3 0x01030000 +#define CONFIG_SYS_DDRCMD_EN_DLL 0x01010000 +#define CONFIG_SYS_DDRCMD_RFSH 0x01080000 #define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432 -#define CONFIG_SYS_MICRON_OCD_DEFAULT 0x01010780 +#define CONFIG_SYS_DDRCMD_OCD_DEFAULT 0x01010780 /* DDR Priority Manager Configuration */ #define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777 |
