ppc4xx: Add Mnemonics for AMCC/IBM DDR2 SDRAM Controller

This patch completes the preprocessor mneomics for the IBM DDR2 SDRAM
controller registers (MODT and INITPLR) used by the
PowerPC405EX(r). The MMODE and MEMODE registers are unified with their
peer values used for the INITPLR MR and EMR registers,
respectively. Finally, a spelling typo is correct (MANUEL to MANUAL).

With these mnemonics in place, the CFG_SDRAM0_* magic numbers for
Kilauea are replaced by equivalent mnemonics to make it easier to
compare and contrast other 405EX(r)-based boards (e.g. during board
bring-up).

Finally, unified the SDRAM controller register dump routine such that
it can be used across all processor variants that utilize the IBM DDR2
SDRAM controller core. It produces output of the form:

	PPC4xx IBM DDR2 Register Dump:
		...
	        SDRAM_MB0CF[40] = 0x00006701
		...

which is '<mnemonic>[<DCR #>] = <value>'. The DCR number is included
since it is not uncommon that the DCR values in header files get mixed
up and it helps to validate, at a glance, they match what is printed
in the user manual.

Tested on:
  AMCC Kilauea/Haleakala:
  - NFS Linux Boot: PASSED
  - NAND Linux Boot: PASSED

Signed-off-by: Grant Erickson <gerickson@nuovations.com>
Signed-off-by: Stefan Roese <sr@denx.de>

1 files changed, 115 insertions, 30 deletions

diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h
index 9c1a3a4c1e..f3d048cb7e 100644
--- a/include/configs/kilauea.h
+++ b/include/configs/kilauea.h
@@ -233,39 +233,124 @@
 #define CFG_SDRAM0_MB1CF	SDRAM_RXBAS_SDBE_DISABLE
 #define CFG_SDRAM0_MB2CF	SDRAM_RXBAS_SDBE_DISABLE
 #define CFG_SDRAM0_MB3CF	SDRAM_RXBAS_SDBE_DISABLE
-#define CFG_SDRAM0_MCOPT1	0x04322000
+#define CFG_SDRAM0_MCOPT1	(SDRAM_MCOPT1_PMU_OPEN		| \
+				 SDRAM_MCOPT1_8_BANKS		| \
+				 SDRAM_MCOPT1_DDR2_TYPE		| \
+				 SDRAM_MCOPT1_QDEP		| \
+				 SDRAM_MCOPT1_DCOO_DISABLED)
 #define CFG_SDRAM0_MCOPT2	0x00000000
-#define CFG_SDRAM0_MODT0	0x01800000
+#define CFG_SDRAM0_MODT0	(SDRAM_MODT_EB0W_ENABLE | \
+				 SDRAM_MODT_EB0R_ENABLE)
 #define CFG_SDRAM0_MODT1	0x00000000
-#define CFG_SDRAM0_CODT		0x0080f837
-#define CFG_SDRAM0_RTR		0x06180000
-#define CFG_SDRAM0_INITPLR0	0xa8380000
-#define CFG_SDRAM0_INITPLR1	0x81900400
-#define CFG_SDRAM0_INITPLR2	0x81020000
-#define CFG_SDRAM0_INITPLR3	0x81030000
-#define CFG_SDRAM0_INITPLR4	0x81010404
-#define CFG_SDRAM0_INITPLR5	0x81000542
-#define CFG_SDRAM0_INITPLR6	0x81900400
-#define CFG_SDRAM0_INITPLR7	0x8D080000
-#define CFG_SDRAM0_INITPLR8	0x8D080000
-#define CFG_SDRAM0_INITPLR9	0x8D080000
-#define CFG_SDRAM0_INITPLR10	0x8D080000
-#define CFG_SDRAM0_INITPLR11	0x81000442
-#define CFG_SDRAM0_INITPLR12	0x81010780
-#define CFG_SDRAM0_INITPLR13	0x81010400
-#define CFG_SDRAM0_INITPLR14	0x00000000
-#define CFG_SDRAM0_INITPLR15	0x00000000
-#define CFG_SDRAM0_RQDC		0x80000038
-#define CFG_SDRAM0_RFDC		0x00000209
-#define CFG_SDRAM0_RDCC		0x40000000
-#define CFG_SDRAM0_DLCR		0x030000a5
-#define CFG_SDRAM0_CLKTR	0x80000000
+#define CFG_SDRAM0_CODT		(SDRAM_CODT_RK0R_ON		| \
+				 SDRAM_CODT_CKLZ_36OHM		| \
+				 SDRAM_CODT_DQS_1_8_V_DDR2	| \
+				 SDRAM_CODT_IO_NMODE)
+#define CFG_SDRAM0_RTR		SDRAM_RTR_RINT_ENCODE(1560)
+#define CFG_SDRAM0_INITPLR0	(SDRAM_INITPLR_ENABLE			| \
+		SDRAM_INITPLR_IMWT_ENCODE(80)				| \
+		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_NOP))
+#define CFG_SDRAM0_INITPLR1	(SDRAM_INITPLR_ENABLE			| \
+		SDRAM_INITPLR_IMWT_ENCODE(3)				| \
+		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE)		| \
+		SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR)			| \
+		SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
+#define CFG_SDRAM0_INITPLR2	(SDRAM_INITPLR_ENABLE			| \
+		SDRAM_INITPLR_IMWT_ENCODE(2)				| \
+		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)		| \
+		SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR2)			| \
+		SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR2_TEMP_COMMERCIAL))
+#define CFG_SDRAM0_INITPLR3	(SDRAM_INITPLR_ENABLE			| \
+		SDRAM_INITPLR_IMWT_ENCODE(2)				| \
+		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)		| \
+		SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR3)			| \
+		SDRAM_INITPLR_IMA_ENCODE(0))
+#define CFG_SDRAM0_INITPLR4	(SDRAM_INITPLR_ENABLE			| \
+		SDRAM_INITPLR_IMWT_ENCODE(2)				| \
+		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)		| \
+		SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR)			| \
+		SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_DQS_DISABLE | \
+					 JEDEC_MA_EMR_RTT_75OHM))
+#define CFG_SDRAM0_INITPLR5	(SDRAM_INITPLR_ENABLE			| \
+		SDRAM_INITPLR_IMWT_ENCODE(2)				| \
+		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)		| \
+		SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR)			| \
+		SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
+					 JEDEC_MA_MR_CL_DDR2_4_0_CLK | \
+					 JEDEC_MA_MR_BLEN_4 | \
+					 JEDEC_MA_MR_DLL_RESET))
+#define CFG_SDRAM0_INITPLR6	(SDRAM_INITPLR_ENABLE			| \
+		SDRAM_INITPLR_IMWT_ENCODE(3)				| \
+		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE)		| \
+		SDRAM_INITPLR_IBA_ENCODE(0x0)				| \
+		SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
+#define CFG_SDRAM0_INITPLR7	(SDRAM_INITPLR_ENABLE			| \
+		SDRAM_INITPLR_IMWT_ENCODE(26)				| \
+		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
+#define CFG_SDRAM0_INITPLR8	(SDRAM_INITPLR_ENABLE			| \
+		SDRAM_INITPLR_IMWT_ENCODE(26)				| \
+		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
+#define CFG_SDRAM0_INITPLR9	(SDRAM_INITPLR_ENABLE			| \
+		SDRAM_INITPLR_IMWT_ENCODE(26)				| \
+		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
+#define CFG_SDRAM0_INITPLR10	(SDRAM_INITPLR_ENABLE			| \
+		SDRAM_INITPLR_IMWT_ENCODE(26)				| \
+		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
+#define CFG_SDRAM0_INITPLR11	(SDRAM_INITPLR_ENABLE			| \
+		SDRAM_INITPLR_IMWT_ENCODE(2)				| \
+		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)		| \
+		SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR)			| \
+		SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
+					 JEDEC_MA_MR_CL_DDR2_4_0_CLK | \
+					 JEDEC_MA_MR_BLEN_4))
+#define CFG_SDRAM0_INITPLR12	(SDRAM_INITPLR_ENABLE			| \
+		SDRAM_INITPLR_IMWT_ENCODE(2)				| \
+		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)		| \
+		SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR)			| \
+		SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_ENTER	| \
+					 JEDEC_MA_EMR_RDQS_DISABLE | \
+					 JEDEC_MA_EMR_DQS_DISABLE | \
+					 JEDEC_MA_EMR_RTT_DISABLED | \
+					 JEDEC_MA_EMR_ODS_NORMAL))
+#define CFG_SDRAM0_INITPLR13	(SDRAM_INITPLR_ENABLE			| \
+		SDRAM_INITPLR_IMWT_ENCODE(2)				| \
+		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)		| \
+		SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR)			| \
+		SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_EXIT | \
+					 JEDEC_MA_EMR_RDQS_DISABLE | \
+					 JEDEC_MA_EMR_DQS_DISABLE | \
+					 JEDEC_MA_EMR_RTT_DISABLED | \
+					 JEDEC_MA_EMR_ODS_NORMAL))
+#define CFG_SDRAM0_INITPLR14	(SDRAM_INITPLR_DISABLE)
+#define CFG_SDRAM0_INITPLR15	(SDRAM_INITPLR_DISABLE)
+#define CFG_SDRAM0_RQDC		(SDRAM_RQDC_RQDE_ENABLE | \
+				 SDRAM_RQDC_RQFD_ENCODE(56))
+#define CFG_SDRAM0_RFDC		SDRAM_RFDC_RFFD_ENCODE(521)
+#define CFG_SDRAM0_RDCC		(SDRAM_RDCC_RDSS_T2)
+#define CFG_SDRAM0_DLCR		(SDRAM_DLCR_DCLM_AUTO		| \
+				 SDRAM_DLCR_DLCS_CONT_DONE	| \
+				 SDRAM_DLCR_DLCV_ENCODE(165))
+#define CFG_SDRAM0_CLKTR	(SDRAM_CLKTR_CLKP_180_DEG_ADV)
 #define CFG_SDRAM0_WRDTR	0x00000000
-#define CFG_SDRAM0_SDTR1	0x80201000
-#define CFG_SDRAM0_SDTR2	0x32204232
-#define CFG_SDRAM0_SDTR3	0x080b0d1a
-#define CFG_SDRAM0_MMODE	0x00000442
-#define CFG_SDRAM0_MEMODE	0x00000404
+#define CFG_SDRAM0_SDTR1	(SDRAM_SDTR1_LDOF_2_CLK	| \
+				 SDRAM_SDTR1_RTW_2_CLK	| \
+				 SDRAM_SDTR1_RTRO_1_CLK)
+#define CFG_SDRAM0_SDTR2	(SDRAM_SDTR2_RCD_3_CLK		| \
+				 SDRAM_SDTR2_WTR_2_CLK		| \
+				 SDRAM_SDTR2_XSNR_32_CLK	| \
+				 SDRAM_SDTR2_WPC_4_CLK		| \
+				 SDRAM_SDTR2_RPC_2_CLK		| \
+				 SDRAM_SDTR2_RP_3_CLK		| \
+				 SDRAM_SDTR2_RRD_2_CLK)
+#define CFG_SDRAM0_SDTR3	(SDRAM_SDTR3_RAS_ENCODE(8)	| \
+				 SDRAM_SDTR3_RC_ENCODE(11)	| \
+				 SDRAM_SDTR3_XCS		| \
+				 SDRAM_SDTR3_RFC_ENCODE(26))
+#define CFG_SDRAM0_MMODE	(SDRAM_MMODE_WR_DDR2_3_CYC | \
+				 SDRAM_MMODE_DCL_DDR2_4_0_CLK | \
+				 SDRAM_MMODE_BLEN_4)
+#define CFG_SDRAM0_MEMODE	(SDRAM_MEMODE_DQS_DISABLE | \
+				 SDRAM_MEMODE_RTT_75OHM)
 
 /*-----------------------------------------------------------------------
  * I2C