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| author | Stefan Roese <sr@denx.de> | 2015-01-19 11:33:46 +0100 |
|---|---|---|
| committer | Luka Perkov <luka.perkov@sartura.hr> | 2015-02-06 17:24:46 +0100 |
| commit | 2554167cc158001cd1befb93e10829fc534bfada (patch) | |
| tree | b464088dd1d8743bc817cbb9378f10069dea63f5 /include/configs/db-mv784mp-gp.h | |
| parent | e7778ec153e279e451bf7c55c05c76e76b095875 (diff) | |
| download | talos-obmc-uboot-2554167cc158001cd1befb93e10829fc534bfada.tar.gz talos-obmc-uboot-2554167cc158001cd1befb93e10829fc534bfada.zip | |
arm: db-mv784mp-gp: Enable SPL to include DDR training code into U-Boot
This patch adds SPL support to the db-mv784mp-gp eval board.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
Diffstat (limited to 'include/configs/db-mv784mp-gp.h')
| -rw-r--r-- | include/configs/db-mv784mp-gp.h | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h index cb03e33b6e..1683a1582f 100644 --- a/include/configs/db-mv784mp-gp.h +++ b/include/configs/db-mv784mp-gp.h @@ -11,6 +11,8 @@ * High Level Configuration Options (easy to change) */ #define CONFIG_ARMADA_XP /* SOC Family Name */ +#define CONFIG_DB_784MP_GP /* Board target name for DDR training */ + #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ #define CONFIG_SYS_GENERIC_BOARD #define CONFIG_DISPLAY_BOARDINFO_LATE @@ -65,4 +67,51 @@ */ #include "mv-common.h" +/* + * Memory layout while starting into the bin_hdr via the + * BootROM: + * + * 0x4000.4000 - 0x4003.4000 headers space (192KiB) + * 0x4000.4030 bin_hdr start address + * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) + * 0x4007.fffc BootROM stack top + * + * The address space between 0x4007.fffc and 0x400f.fff is not locked in + * L2 cache thus cannot be used. + */ + +/* SPL */ +/* Defines for SPL */ +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_TEXT_BASE 0x40004030 +#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) + +#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) +#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) + +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ + CONFIG_SPL_BSS_MAX_SIZE) +#define CONFIG_SYS_SPL_MALLOC_SIZE (16 << 10) + +#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) +#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_LDSCRIPT "arch/arm/mvebu-common/u-boot-spl.lds" + +/* SPL related SPI defines */ +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_LOAD +#define CONFIG_SPL_SPI_BUS 0 +#define CONFIG_SPL_SPI_CS 0 +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 + +/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ +#define CONFIG_SYS_MVEBU_DDR +#define CONFIG_SPD_EEPROM 0x4e + #endif /* _CONFIG_DB_MV7846MP_GP_H */ |
