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| author | Simon Glass <sjg@chromium.org> | 2013-04-17 16:13:36 +0000 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2013-05-13 13:33:21 -0700 |
| commit | e761ecdbb83e3151ffea5b531523256c57e62527 (patch) | |
| tree | cbd44285af8784933d8c09caba2f0f8208d1856b /include/configs/coreboot.h | |
| parent | 7949703a9582ec60cf841c595acd3bbe86933cd3 (diff) | |
| download | talos-obmc-uboot-e761ecdbb83e3151ffea5b531523256c57e62527.tar.gz talos-obmc-uboot-e761ecdbb83e3151ffea5b531523256c57e62527.zip | |
x86: Add TSC timer
This timer runs at a rate that can be calculated, well over 100MHz. It is
ideal for accurate timing and does not need interrupt servicing.
Tidy up some old broken and unneeded implementations at the same time.
To provide a consistent view of boot time, we use the same time
base as coreboot. Use the base timestamp supplied by coreboot
as U-Boot's base time.
Signed-off-by: Simon Glass <sjg@chromium.org>base
Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'include/configs/coreboot.h')
| -rw-r--r-- | include/configs/coreboot.h | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h index 5bacc77bb5..99408dcc58 100644 --- a/include/configs/coreboot.h +++ b/include/configs/coreboot.h @@ -38,7 +38,6 @@ #define CONFIG_SHOW_BOOT_PROGRESS #define CONFIG_LAST_STAGE_INIT #define CONFIG_SYS_VSNPRINTF -#define CONFIG_INTEL_CORE_ARCH /* Sandy bridge and ivy bridge chipsets. */ #define CONFIG_ZBOOT_32 #define CONFIG_PHYSMEM #define CONFIG_SYS_EARLY_PCI_INIT @@ -218,7 +217,6 @@ #define CONFIG_SYS_MEMTEST_END 0x01000000 #define CONFIG_SYS_LOAD_ADDR 0x100000 #define CONFIG_SYS_HZ 1000 -#define CONFIG_SYS_X86_ISR_TIMER /*----------------------------------------------------------------------- * SDRAM Configuration @@ -235,7 +233,7 @@ * CPU Features */ -#define CONFIG_SYS_GENERIC_TIMER +#define CONFIG_SYS_X86_TSC_TIMER #define CONFIG_SYS_PCAT_INTERRUPTS #define CONFIG_SYS_NUM_IRQS 16 |
