diff options
| author | Peter Tyser <ptyser@xes-inc.com> | 2010-10-22 00:20:22 -0500 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2010-10-22 02:17:02 -0500 |
| commit | 9660c5de74aae900077c3769d7d18b39a124d9d5 (patch) | |
| tree | aacf55f23fae492e82107417ceb738cb14d61ea3 /include/configs/XPEDITE5370.h | |
| parent | 4c66447ae77e52edd5d9df33bd8a3457860713b8 (diff) | |
| download | talos-obmc-uboot-9660c5de74aae900077c3769d7d18b39a124d9d5.tar.gz talos-obmc-uboot-9660c5de74aae900077c3769d7d18b39a124d9d5.zip | |
xes: Use common PCI initialization code
Common Freescale code for PCI initialization now exists, so migrate X-ES
boards to use it.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'include/configs/XPEDITE5370.h')
| -rw-r--r-- | include/configs/XPEDITE5370.h | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/include/configs/XPEDITE5370.h b/include/configs/XPEDITE5370.h index 629dc0d89c..01047c85ee 100644 --- a/include/configs/XPEDITE5370.h +++ b/include/configs/XPEDITE5370.h @@ -334,18 +334,18 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); * Memory space is mapped 1-1, but I/O space must start from 0. */ /* PCIE1 - VPX P1 */ -#define CONFIG_SYS_PCIE1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE +#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS #define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */ -#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ /* PCIE2 - PEX8518 */ -#define CONFIG_SYS_PCIE2_MEM_BASE 0xc0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BASE +#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */ |
