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| author | Jon Loeliger <jdl@freescale.com> | 2007-07-08 13:46:18 -0500 |
|---|---|---|
| committer | Jon Loeliger <jdl@freescale.com> | 2007-07-08 16:05:28 -0500 |
| commit | 348f258f24253433e4a2302a0bbceb6740a67246 (patch) | |
| tree | 45ba7b5fb90325cd20dd680d4da4711746e6937f /include/configs/IDS8247.h | |
| parent | 6c4f4da9bfc9f9403f54fce678ed0364b7c86a6a (diff) | |
| download | talos-obmc-uboot-348f258f24253433e4a2302a0bbceb6740a67246.tar.gz talos-obmc-uboot-348f258f24253433e4a2302a0bbceb6740a67246.zip | |
include/configs: Use new CONFIG_CMD_* in various [IJKL]* named board config files.
Signed-off-by: Jon Loeliger <jdl@freescale.com>
Diffstat (limited to 'include/configs/IDS8247.h')
| -rw-r--r-- | include/configs/IDS8247.h | 27 |
1 files changed, 15 insertions, 12 deletions
diff --git a/include/configs/IDS8247.h b/include/configs/IDS8247.h index 29eb874dbf..45a96ae787 100644 --- a/include/configs/IDS8247.h +++ b/include/configs/IDS8247.h @@ -161,22 +161,25 @@ #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_NFS | \ - CFG_CMD_NAND | \ - CFG_CMD_I2C | \ - CFG_CMD_SNTP ) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_NFS +#define CONFIG_CMD_NAND +#define CONFIG_CMD_I2C +#define CONFIG_CMD_SNTP + /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -234,7 +237,7 @@ * NAND-FLASH stuff *----------------------------------------------------------------------- */ -#if (CONFIG_COMMANDS & CFG_CMD_NAND) +#if defined(CONFIG_CMD_NAND) #define CFG_NAND_LEGACY #define CFG_NAND0_BASE 0xE1000000 @@ -355,7 +358,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif @@ -474,7 +477,7 @@ #define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH_SIZE) |\ ORxG_SCY_6_CLK ) -#if (CONFIG_COMMANDS & CFG_CMD_NAND) +#if defined(CONFIG_CMD_NAND) /* Bank 1 - NAND Flash */ #define CFG_NAND_BASE CFG_NAND0_BASE |
