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| author | Mike Frysinger <vapier@gentoo.org> | 2009-11-11 19:08:33 -0500 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2010-01-17 09:17:26 -0500 |
| commit | dc6bc645e0cc1939b31cc54346415cf8e0dffc88 (patch) | |
| tree | 7f1e0ee52bbe5f793948921e4f1cead6e478c348 /include/asm-blackfin/mach-bf527/BF522_def.h | |
| parent | b7659ef2e764f62fc334f0d970721496823e4888 (diff) | |
| download | talos-obmc-uboot-dc6bc645e0cc1939b31cc54346415cf8e0dffc88.tar.gz talos-obmc-uboot-dc6bc645e0cc1939b31cc54346415cf8e0dffc88.zip | |
Blackfin: fix L1 Instruction sizes on BF52x/BF54x
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'include/asm-blackfin/mach-bf527/BF522_def.h')
| -rw-r--r-- | include/asm-blackfin/mach-bf527/BF522_def.h | 15 |
1 files changed, 0 insertions, 15 deletions
diff --git a/include/asm-blackfin/mach-bf527/BF522_def.h b/include/asm-blackfin/mach-bf527/BF522_def.h index 44143ba893..bc05029aac 100644 --- a/include/asm-blackfin/mach-bf527/BF522_def.h +++ b/include/asm-blackfin/mach-bf527/BF522_def.h @@ -119,20 +119,5 @@ #define TPERIOD 0xFFE03004 /* Core Timer Period Register */ #define TSCALE 0xFFE03008 /* Core Timer Scale Register */ #define TCOUNT 0xFFE0300C /* Core Timer Count Register */ -#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */ -#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1) -#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE) -#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */ -#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1) -#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE) -#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */ -#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1) -#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) -#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ -#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) -#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) -#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ -#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) -#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE) #endif /* __BFIN_DEF_ADSP_BF522_proc__ */ |
