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| author | Wolfgang Denk <wd@pollux.(none)> | 2005-09-25 18:41:04 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@pollux.(none)> | 2005-09-25 18:41:04 +0200 |
| commit | 49a7581c6ced35379ec3c450bb60fe736db9d733 (patch) | |
| tree | 7f3d964bd45d09f62122231ac7e26c61b120349f /include/asm-arm/arch-arm1136/omap2420.h | |
| parent | 8e2be51de8dd03c1ce4d06cbb18ad06133d47cd5 (diff) | |
| download | talos-obmc-uboot-49a7581c6ced35379ec3c450bb60fe736db9d733.tar.gz talos-obmc-uboot-49a7581c6ced35379ec3c450bb60fe736db9d733.zip | |
OMAP242x H4 board update
- fix for ES2 differences.
- switch to using the cfi_flash driver.
- fix SRAM build address.
- fix for GP device operation.
- unlock SRAM for GP devices.
- display more device information.
- fix potential deadlock in omap24xx_i2c driver.
- fix DLL load values to match dpllout*1 operation.
- fix 2nd chip select init for combo DDR device.
- add support for CFI Intel 28F256L18 on H4 board.
Patch by Richard Woodruff, 03 Mar 2005
Diffstat (limited to 'include/asm-arm/arch-arm1136/omap2420.h')
| -rw-r--r-- | include/asm-arm/arch-arm1136/omap2420.h | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/include/asm-arm/arch-arm1136/omap2420.h b/include/asm-arm/arch-arm1136/omap2420.h index eba385cea3..7a7aae6b0e 100644 --- a/include/asm-arm/arch-arm1136/omap2420.h +++ b/include/asm-arm/arch-arm1136/omap2420.h @@ -37,13 +37,25 @@ #define A_WRITEPERM0 0x68005058 #define GP_DEVICE (BIT8|BIT9) +/* L3 Firewall */ +#define A_REQINFOPERM0 0x68005048 +#define A_READPERM0 0x68005050 +#define A_WRITEPERM0 0x68005058 + /* CONTROL */ #define OMAP2420_CTRL_BASE (0x48000000) #define CONTROL_STATUS (OMAP2420_CTRL_BASE + 0x2F8) +/* device type */ +#define TST_DEVICE 0x0 +#define EMU_DEVICE 0x1 +#define HS_DEVICE 0x2 +#define GP_DEVICE 0x3 + /* TAP information */ #define OMAP2420_TAP_BASE (0x48014000) #define TAP_IDCODE_REG (OMAP2420_TAP_BASE+0x204) +#define PRODUCTION_ID (OMAP2420_TAP_BASE+0x208) /* GPMC */ #define OMAP2420_GPMC_BASE (0x6800A000) @@ -76,6 +88,7 @@ #define OMAP2420_SDRC_BASE 0x68009000 #define SDRC_SYSCONFIG (OMAP2420_SDRC_BASE+0x10) #define SDRC_STATUS (OMAP2420_SDRC_BASE+0x14) +#define SDRC_CS_CFG (OMAP2420_SDRC_BASE+0x40) #define SDRC_SHARING (OMAP2420_SDRC_BASE+0x44) #define SDRC_DLLA_CTRL (OMAP2420_SDRC_BASE+0x60) #define SDRC_DLLB_CTRL (OMAP2420_SDRC_BASE+0x68) |
