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| author | Hans de Goede <hdegoede@redhat.com> | 2014-12-23 18:39:52 +0100 |
|---|---|---|
| committer | Hans de Goede <hdegoede@redhat.com> | 2015-01-14 14:56:39 +0100 |
| commit | e84007933ad411d548d2be5c133e3ab065e2fe6b (patch) | |
| tree | f402c816c6f6221a147132c11804f594599f7d28 /drivers | |
| parent | 5489ebc7af2e0f46eb5e818e2dc646d03bd96541 (diff) | |
| download | talos-obmc-uboot-e84007933ad411d548d2be5c133e3ab065e2fe6b.tar.gz talos-obmc-uboot-e84007933ad411d548d2be5c133e3ab065e2fe6b.zip | |
sunxi: video: Move sunxi_drc_init
Move sunxi_drc_init to directly above sunxi_engines_init, to avoid
unnecessary #ifdef-ery in later patches.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/video/sunxi_display.c | 26 |
1 files changed, 12 insertions, 14 deletions
diff --git a/drivers/video/sunxi_display.c b/drivers/video/sunxi_display.c index e4f95d49a9..ad38f162fd 100644 --- a/drivers/video/sunxi_display.c +++ b/drivers/video/sunxi_display.c @@ -473,18 +473,6 @@ static void sunxi_lcdc_tcon1_mode_set(const struct ctfb_res_modes *mode, sunxi_lcdc_pll_set(1, mode->pixclock_khz, clk_div, clk_double); } -#ifdef CONFIG_MACH_SUN6I -static void sunxi_drc_init(void) -{ - struct sunxi_ccm_reg * const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - - /* On sun6i the drc must be clocked even when in pass-through mode */ - setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DRC0); - clock_set_de_mod_clock(&ccm->iep_drc0_clk_cfg, 300000000); -} -#endif - static void sunxi_hdmi_setup_info_frames(const struct ctfb_res_modes *mode) { struct sunxi_hdmi_reg * const hdmi = @@ -593,13 +581,23 @@ static void sunxi_hdmi_enable(void) setbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_ENABLE); } +static void sunxi_drc_init(void) +{ +#ifdef CONFIG_MACH_SUN6I + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + /* On sun6i the drc must be clocked even when in pass-through mode */ + setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DRC0); + clock_set_de_mod_clock(&ccm->iep_drc0_clk_cfg, 300000000); +#endif +} + static void sunxi_engines_init(void) { sunxi_composer_init(); sunxi_lcdc_init(); -#ifdef CONFIG_MACH_SUN6I sunxi_drc_init(); -#endif } static void sunxi_mode_set(const struct ctfb_res_modes *mode, |
