Initial support for MPC8641 HPCN board.

3 files changed, 83 insertions, 8 deletions

diff --git a/drivers/pci_auto.c b/drivers/pci_auto.c
index 15f74328f0..3c958d3b95 100644
--- a/drivers/pci_auto.c
+++ b/drivers/pci_auto.c
@@ -186,7 +186,7 @@ static void pciauto_prescan_setup_bridge(struct pci_controller *hose,
 	} else {
 		/* We don't support prefetchable memory for now, so disable */
 		pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000);
-		pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x1000);
+		pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x1);
 	}
 
 	if (pci_io) {
diff --git a/drivers/tsec.c b/drivers/tsec.c
index 7ec565ca67..18778c270a 100644
--- a/drivers/tsec.c
+++ b/drivers/tsec.c
@@ -14,6 +14,7 @@
 
 #include <config.h>
 #include <mpc85xx.h>
+#include <mpc86xx.h>
 #include <common.h>
 #include <malloc.h>
 #include <net.h>
@@ -74,27 +75,33 @@ struct tsec_info_struct {
 static struct tsec_info_struct tsec_info[] = {
 #if defined(CONFIG_MPC85XX_TSEC1) || defined(CONFIG_MPC83XX_TSEC1)
 	{TSEC1_PHY_ADDR, TSEC_GIGABIT, TSEC1_PHYIDX},
+#elif defined(CONFIG_MPC86XX_TSEC1)
+	{TSEC1_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC1_PHYIDX},
 #else
 	{ 0, 0, 0},
 #endif
 #if defined(CONFIG_MPC85XX_TSEC2) || defined(CONFIG_MPC83XX_TSEC2)
 	{TSEC2_PHY_ADDR, TSEC_GIGABIT, TSEC2_PHYIDX},
+#elif defined(CONFIG_MPC86XX_TSEC2)
+        {TSEC2_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC2_PHYIDX},
 #else
 	{ 0, 0, 0},
 #endif
 #ifdef CONFIG_MPC85XX_FEC
 	{FEC_PHY_ADDR, 0, FEC_PHYIDX},
 #else
-#    if defined(CONFIG_MPC85XX_TSEC3) || defined(CONFIG_MPC83XX_TSEC3)
+#if defined(CONFIG_MPC85XX_TSEC3) || defined(CONFIG_MPC83XX_TSEC3) || defined(CONFIG_MPC86XX_TSEC3)
 	{TSEC3_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC3_PHYIDX},
-#    else
+#else
 	{ 0, 0, 0},
-#    endif
-#    if defined(CONFIG_MPC85XX_TSEC4) || defined(CONFIG_MPC83XX_TSEC4)
+#endif
+#if defined(CONFIG_MPC85XX_TSEC4) || defined(CONFIG_MPC83XX_TSEC4)
 	{TSEC4_PHY_ADDR, TSEC_REDUCED, TSEC4_PHYIDX},
-#    else
+#elif defined(CONFIG_MPC86XX_TSEC4)
+       {TSEC4_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC4_PHYIDX},
+#else
 	{ 0, 0, 0},
-#    endif
+#endif
 #endif
 };
 
@@ -467,6 +474,32 @@ uint mii_parse_cis8201(uint mii_reg, struct tsec_private *priv)
 
 	return 0;
 }
+/* Parse the vsc8244's status register for speed and duplex
+ * information */
+uint mii_parse_vsc8244(uint mii_reg, struct tsec_private *priv)
+{
+        uint speed;
+                                                                                
+        if(mii_reg & MIIM_VSC8244_AUXCONSTAT_DUPLEX)
+                priv->duplexity = 1;
+        else
+                priv->duplexity = 0;
+                                                                                
+        speed = mii_reg & MIIM_VSC8244_AUXCONSTAT_SPEED;
+        switch(speed) {
+                case MIIM_VSC8244_AUXCONSTAT_GBIT:
+                        priv->speed = 1000;
+                        break;
+                case MIIM_VSC8244_AUXCONSTAT_100:
+                        priv->speed = 100;
+                        break;
+                default:
+                        priv->speed = 10;
+                        break;
+        }
+                                                                                
+        return 0;
+}
 
 
 /* Parse the DM9161's status register for speed and duplex
@@ -859,6 +892,29 @@ struct phy_info phy_info_cis8201 = {
 		{miim_end,}
 	},
 };
+struct phy_info phy_info_VSC8244 = {
+        0x3f1b,
+        "Vitesse VSC8244",
+        6,
+        (struct phy_cmd[]) { /* config */
+        /* Override PHY config settings */
+                /* Configure some basic stuff */
+        	{MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
+                {miim_end,}
+        },
+        (struct phy_cmd[]) { /* startup */
+                /* Read the Status (2x to make sure link is right) */
+                {MIIM_STATUS, miim_read, NULL},
+                /* Auto-negotiate */
+                {MIIM_STATUS, miim_read, &mii_parse_sr},
+                /* Read the status */
+                {MIIM_VSC8244_AUX_CONSTAT, miim_read, &mii_parse_vsc8244},
+                {miim_end,}
+        },
+        (struct phy_cmd[]) { /* shutdown */
+                {miim_end,}
+        },
+};
 
 
 struct phy_info phy_info_dm9161 = {
@@ -1001,6 +1057,7 @@ struct phy_info *phy_info[] = {
 	&phy_info_M88E1111S,
 	&phy_info_dm9161,
 	&phy_info_lxt971,
+	&phy_info_VSC8244,
 	&phy_info_dp83865,
 	NULL
 };
diff --git a/drivers/tsec.h b/drivers/tsec.h
index b55b2992b2..31f18675fb 100644
--- a/drivers/tsec.h
+++ b/drivers/tsec.h
@@ -27,7 +27,7 @@
 #define TSEC_SIZE	0x01000
 
 /* FIXME:  Should these be pushed back to 83xx and 85xx config files? */
-#if defined(CONFIG_MPC85xx)
+#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
     #define TSEC_BASE_ADDR	(CFG_IMMR + CFG_TSEC1_OFFSET)
 #elif defined(CONFIG_MPC83XX)
     #define TSEC_BASE_ADDR	(CFG_IMMRBAR + CFG_TSEC1_OFFSET)
@@ -133,6 +133,24 @@
 #define MIIM_GBIT_CON		0x09
 #define MIIM_GBIT_CON_ADVERT	0x0e00
 
+/* Entry for Vitesse VSC8244 regs starts here */
+/* Vitesse VSC8244 Auxiliary Control/Status Register */
+#define MIIM_VSC8244_AUX_CONSTAT        0x1c
+#define MIIM_VSC8244_AUXCONSTAT_INIT    0x0000
+#define MIIM_VSC8244_AUXCONSTAT_DUPLEX  0x0020
+#define MIIM_VSC8244_AUXCONSTAT_SPEED   0x0018
+#define MIIM_VSC8244_AUXCONSTAT_GBIT    0x0010
+#define MIIM_VSC8244_AUXCONSTAT_100     0x0008
+#define MIIM_CONTROL_INIT_LOOPBACK      0x4000
+
+/* Vitesse VSC8244 Extended PHY Control Register 1 */
+#define MIIM_VSC8244_EPHY_CON           0x17
+#define MIIM_VSC8244_EPHYCON_INIT       0x0006
+
+/* Vitesse VSC8244 Serial LED Control Register */
+#define MIIM_VSC8244_LED_CON            0x1b
+#define MIIM_VSC8244_LEDCON_INIT        0xF011
+
 /* 88E1011 PHY Status Register */
 #define MIIM_88E1011_PHY_STATUS         0x11
 #define MIIM_88E1011_PHYSTAT_SPEED      0xc000