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| author | Marek Vasut <marex@denx.de> | 2015-08-01 20:10:23 +0200 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2015-08-08 14:14:26 +0200 |
| commit | a5ba9296710522d1916795a81074cf9d6659d7a0 (patch) | |
| tree | 439697e406783037944acfcc149fd2f488327946 /drivers | |
| parent | 1009e396ddef43da67924d252e9f0dac746ba738 (diff) | |
| download | talos-obmc-uboot-a5ba9296710522d1916795a81074cf9d6659d7a0.tar.gz talos-obmc-uboot-a5ba9296710522d1916795a81074cf9d6659d7a0.zip | |
ddr: altera: sdram: Clean up set_sdr_mp_weight()
Get rid of the constant clrsetbits_le32(), instead prepare the whole
content of the register once and write it at the end of the function.
Signed-off-by: Marek Vasut <marex@denx.de>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/ddr/altera/sdram.c | 37 |
1 files changed, 16 insertions, 21 deletions
diff --git a/drivers/ddr/altera/sdram.c b/drivers/ddr/altera/sdram.c index 8db8dde5dd..f3248055d1 100644 --- a/drivers/ddr/altera/sdram.c +++ b/drivers/ddr/altera/sdram.c @@ -417,31 +417,26 @@ static void set_sdr_fifo_cfg(void) static void set_sdr_mp_weight(void) { - debug("Configuring MPWEIGHT_MPWEIGHT_0\n"); - clrsetbits_le32(&sdr_ctrl->mp_weight0, - SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_MASK, - CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 << + const u32 mp_weight0 = + (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 << SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB); - - clrsetbits_le32(&sdr_ctrl->mp_weight1, - SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_MASK, - CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 << - SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB); - - clrsetbits_le32(&sdr_ctrl->mp_weight1, - SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_MASK, - CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 << + const u32 mp_weight1 = + (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 << + SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 << SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB); - - clrsetbits_le32(&sdr_ctrl->mp_weight2, - SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_MASK, - CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 << + const u32 mp_weight2 = + (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 << SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB); - - clrsetbits_le32(&sdr_ctrl->mp_weight3, - SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_MASK, - CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 << + const u32 mp_weight3 = + (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 << SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB); + + debug("Configuring MPWEIGHT_MPWEIGHT_0\n"); + writel(mp_weight0, &sdr_ctrl->mp_weight0); + writel(mp_weight1, &sdr_ctrl->mp_weight1); + writel(mp_weight2, &sdr_ctrl->mp_weight2); + writel(mp_weight3, &sdr_ctrl->mp_weight3); } static void set_sdr_mp_pacing(void) |
