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authorDan Murphy <dmurphy@ti.com>2013-10-11 12:28:17 -0500
committerMarek Vasut <marex@denx.de>2013-10-20 23:42:41 +0200
commit834e91af432479e3808e9cbd1d38199f724fc5aa (patch)
tree1ee55275e290c7b2bc4ec4523d8ad1ed1eba8d5b /drivers
parentba55453ccf6d82c46b9f3eef5b958aac58adb6fb (diff)
downloadtalos-obmc-uboot-834e91af432479e3808e9cbd1d38199f724fc5aa.tar.gz
talos-obmc-uboot-834e91af432479e3808e9cbd1d38199f724fc5aa.zip
usb: dra7xx: Add support for dra7xx xhci USB host
Add the support for the dra7xx xhci usb host. dra7xx does not contain an EHCI controller so the headers can be removed from the board file. The xHCI host on dra7xx is connected to a usb2 phy so need to add support to enable those clocks. Signed-off-by: Dan Murphy <dmurphy@ti.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/usb/host/xhci-omap.c6
-rw-r--r--drivers/usb/phy/omap_usb_phy.c45
2 files changed, 45 insertions, 6 deletions
diff --git a/drivers/usb/host/xhci-omap.c b/drivers/usb/host/xhci-omap.c
index 7292ed817e..f6099ac173 100644
--- a/drivers/usb/host/xhci-omap.c
+++ b/drivers/usb/host/xhci-omap.c
@@ -98,9 +98,7 @@ static int omap_xhci_core_init(struct omap_xhci *omap)
{
int ret = 0;
- omap_enable_phy_clocks(omap);
-
- omap_usb3_phy_init(omap->usb3_phy);
+ omap_enable_phy(omap);
ret = dwc3_core_init(omap->dwc3_reg);
if (ret) {
@@ -116,7 +114,7 @@ static int omap_xhci_core_init(struct omap_xhci *omap)
static void omap_xhci_core_exit(struct omap_xhci *omap)
{
- usb3_phy_power(0);
+ usb_phy_power(0);
}
int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
diff --git a/drivers/usb/phy/omap_usb_phy.c b/drivers/usb/phy/omap_usb_phy.c
index ed727bf290..f074a88950 100644
--- a/drivers/usb/phy/omap_usb_phy.c
+++ b/drivers/usb/phy/omap_usb_phy.c
@@ -22,6 +22,7 @@
#include "../host/xhci.h"
+#ifdef CONFIG_OMAP_USB3PHY1_HOST
struct usb_dpll_params {
u16 m;
u8 n;
@@ -99,7 +100,7 @@ static void usb3_phy_partial_powerup(struct omap_usb3_phy *phy_regs)
writel(val, (*ctrl)->control_phy_power_usb);
}
-void usb3_phy_power(int on)
+void usb_phy_power(int on)
{
u32 val;
@@ -128,7 +129,7 @@ void omap_usb3_phy_init(struct omap_usb3_phy *phy_regs)
usb3_phy_power(1);
}
-void omap_enable_phy_clocks(struct omap_xhci *omap)
+static void omap_enable_usb3_phy(struct omap_xhci *omap)
{
u32 val;
@@ -176,6 +177,35 @@ void omap_enable_phy_clocks(struct omap_xhci *omap)
setbits_le32((*prcm)->cm_l3init_usb_otg_ss_clkctrl, val);
};
+#endif /* CONFIG_OMAP_USB3PHY1_HOST */
+
+#ifdef CONFIG_OMAP_USB2PHY2_HOST
+static void omap_enable_usb2_phy2(struct omap_xhci *omap)
+{
+ u32 reg, val;
+
+ val = (~USB2PHY_AUTORESUME_EN & USB2PHY_DISCHGDET);
+ writel(val, (*ctrl)->control_srcomp_north_side);
+
+ setbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl,
+ USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
+
+ setbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl,
+ (USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K |
+ OTG_SS_CLKCTRL_MODULEMODE_HW));
+
+ /* This is an undocumented Reserved register */
+ reg = 0x4a0086c0;
+ val = readl(reg);
+ val |= 0x100;
+ setbits_le32(reg, val);
+}
+
+void usb_phy_power(int on)
+{
+ return;
+}
+#endif /* CONFIG_OMAP_USB2PHY2_HOST */
void omap_reset_usb_phy(struct dwc3 *dwc3_reg)
{
@@ -195,3 +225,14 @@ void omap_reset_usb_phy(struct dwc3 *dwc3_reg)
}
+void omap_enable_phy(struct omap_xhci *omap)
+{
+#ifdef CONFIG_OMAP_USB2PHY2_HOST
+ omap_enable_usb2_phy2(omap);
+#endif
+
+#ifdef CONFIG_OMAP_USB3PHY1_HOST
+ omap_enable_usb3_phy(omap);
+ omap_usb3_phy_init(omap->usb3_phy);
+#endif
+}
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