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| author | Gary Jennejohn <garyj@denx.de> | 2007-08-31 15:21:46 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2007-08-31 15:21:46 +0200 |
| commit | 81b73dec16fd1227369a191e725e10044a9d56b8 (patch) | |
| tree | 3d0fe0f95120227c7ced28cc3ff742e35d22dd71 /drivers | |
| parent | 9c02defc29b57945b600714cf61ddfd02b02fb14 (diff) | |
| download | talos-obmc-uboot-81b73dec16fd1227369a191e725e10044a9d56b8.tar.gz talos-obmc-uboot-81b73dec16fd1227369a191e725e10044a9d56b8.zip | |
ppc4xx: (Re-)Enable CONFIG_PCI_PNP on AMCC 440EPx Sequoia
The 440EPx has a problem when the PCI_CACHE_LINE_SIZE register is
set to non-zero, because it doesn't support MRM (memory-read-
multiple) correctly. We now added the possibility to configure
this register in the board config file, so that the default value
of 8 can be overridden.
Here the details of this patch:
o drivers_pci_auto.c: introduce CFG_PCI_CACHE_LINE_SIZE to allow
board-specific settings. As an example the sequoia board requires 0.
Idea from Stefan Roese <sr@denx.de>.
o board/amcc/sequoia/init.S: add a TLB mapping at 0xE8000000 for the
PCI IO-space. Obtained from Stefan Roese <sr@denx.de>.
o include/configs/sequoia.h: turn CONFIG_PCI_PNP back on and set
CFG_PCI_CACHE_LINE_SIZE to 0.
Signed-off-by: Gary Jennejohn <garyj@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/pci_auto.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/drivers/pci_auto.c b/drivers/pci_auto.c index 2378553be5..acfda83ba5 100644 --- a/drivers/pci_auto.c +++ b/drivers/pci_auto.c @@ -28,6 +28,11 @@ #define PCIAUTO_IDE_MODE_MASK 0x05 +/* the user can define CFG_PCI_CACHE_LINE_SIZE to avoid problems */ +#ifndef CFG_PCI_CACHE_LINE_SIZE +#define CFG_PCI_CACHE_LINE_SIZE 8 +#endif + /* * */ @@ -150,7 +155,8 @@ void pciauto_setup_device(struct pci_controller *hose, } pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat); - pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); + pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, + CFG_PCI_CACHE_LINE_SIZE); pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); } |
