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| author | Marek Vasut <marex@denx.de> | 2015-08-01 19:33:40 +0200 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2015-08-08 14:14:25 +0200 |
| commit | 067c853fe6ad67217f444428ccbfa038dfa8522d (patch) | |
| tree | 1ff7bf0757109141220d3a1d7261f435e1a5b5c5 /drivers | |
| parent | f36716971d3700a7b57be331136777bb82392de3 (diff) | |
| download | talos-obmc-uboot-067c853fe6ad67217f444428ccbfa038dfa8522d.tar.gz talos-obmc-uboot-067c853fe6ad67217f444428ccbfa038dfa8522d.zip | |
ddr: altera: sdram: Clean up set_sdr_ctrlcfg()
Get rid of the constant clrsetbits_le32(), instead prepare the whole
content of the register once and write it at the end of the function.
The big plan here is to remove all the CONFIG_HPS_SDR_ macros, hide
them in QTS compatibility layer in board implementation and pass only
a small structure into the driver.
Signed-off-by: Marek Vasut <marex@denx.de>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/ddr/altera/sdram.c | 62 |
1 files changed, 24 insertions, 38 deletions
diff --git a/drivers/ddr/altera/sdram.c b/drivers/ddr/altera/sdram.c index ca685286e0..0bfd564ede 100644 --- a/drivers/ddr/altera/sdram.c +++ b/drivers/ddr/altera/sdram.c @@ -254,18 +254,29 @@ static unsigned sdram_write_verify(unsigned int *addr, unsigned reg_value) static void set_sdr_ctrlcfg(void) { - int addrorder; + u32 addrorder; + u32 ctrl_cfg = + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE << + SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL << + SDR_CTRLGRP_CTRLCFG_MEMBL_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN << + SDR_CTRLGRP_CTRLCFG_ECCEN_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN << + SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN << + SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT << + SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN << + SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS << + SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB); debug("\nConfiguring CTRLCFG\n"); - clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_MEMTYPE_MASK, - CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE << - SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB); - clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_MEMBL_MASK, - CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL << - SDR_CTRLGRP_CTRLCFG_MEMBL_LSB); - - /* SDRAM Failure When Accessing Non-Existent Memory + /* + * SDRAM Failure When Accessing Non-Existent Memory * Set the addrorder field of the SDRAM control register * based on the CSBITs setting. */ @@ -273,46 +284,21 @@ static void set_sdr_ctrlcfg(void) case 1: addrorder = 0; /* chip, row, bank, column */ if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER != 0) - debug("INFO: Changing address order to 0 (chip, row, \ - bank, column)\n"); + debug("INFO: Changing address order to 0 (chip, row, bank, column)\n"); break; case 2: addrorder = 2; /* row, chip, bank, column */ if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER != 2) - debug("INFO: Changing address order to 2 (row, chip, \ - bank, column)\n"); + debug("INFO: Changing address order to 2 (row, chip, bank, column)\n"); break; default: addrorder = CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER; break; } - clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK, - addrorder << SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB); - - clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_ECCEN_MASK, - CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN << - SDR_CTRLGRP_CTRLCFG_ECCEN_LSB); + ctrl_cfg |= addrorder << SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB; - clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_ECCCORREN_MASK, - CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN << - SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB); - - clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_REORDEREN_MASK, - CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN << - SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB); - - clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_STARVELIMIT_MASK, - CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT << - SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB); - - clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK, - CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN << - SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB); - - clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_NODMPINS_MASK, - CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS << - SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB); + writel(ctrl_cfg, &sdr_ctrl->ctrl_cfg); } static void set_sdr_dram_timing1(void) |
