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| author | Hans de Goede <hdegoede@redhat.com> | 2015-08-06 12:08:33 +0200 |
|---|---|---|
| committer | Hans de Goede <hdegoede@redhat.com> | 2015-08-14 08:37:36 +0200 |
| commit | d8d079966f5d5cf00c33986aa505ab90bcb259b2 (patch) | |
| tree | 77b003a3e4bd7d9ee120ece720f64a37533bf520 /drivers/video | |
| parent | 58332f89b63de484024deae402feeafefc9a43e1 (diff) | |
| download | talos-obmc-uboot-d8d079966f5d5cf00c33986aa505ab90bcb259b2.tar.gz talos-obmc-uboot-d8d079966f5d5cf00c33986aa505ab90bcb259b2.zip | |
sunxi: display: Fix composite video out on sun5i
The tv-encoder on sun5i is slightly different compared to the one on
sun4i/sun7i.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Diffstat (limited to 'drivers/video')
| -rw-r--r-- | drivers/video/sunxi_display.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/video/sunxi_display.c b/drivers/video/sunxi_display.c index 7c1ea8f2f6..f5deca35ab 100644 --- a/drivers/video/sunxi_display.c +++ b/drivers/video/sunxi_display.c @@ -485,7 +485,9 @@ static void sunxi_composer_mode_set(const struct ctfb_res_modes *mode, setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_LAYER0_ENABLE); if (mode->vmode == FB_VMODE_INTERLACED) setbits_le32(&de_be->mode, +#ifndef CONFIG_MACH_SUN5I SUNXI_DE_BE_MODE_DEFLICKER_ENABLE | +#endif SUNXI_DE_BE_MODE_INTERLACE_ENABLE); if (sunxi_is_composite()) { @@ -874,6 +876,13 @@ static void sunxi_lcdc_tcon1_mode_set(const struct ctfb_res_modes *mode, SUNXI_LCDC_TCON_VSYNC_MASK | SUNXI_LCDC_TCON_HSYNC_MASK); } + +#ifdef CONFIG_MACH_SUN5I + if (sunxi_is_composite()) + clrsetbits_le32(&lcdc->mux_ctrl, SUNXI_LCDC_MUX_CTRL_SRC0_MASK, + SUNXI_LCDC_MUX_CTRL_SRC0(1)); +#endif + sunxi_lcdc_pll_set(1, mode->pixclock_khz, clk_div, clk_double); } #endif /* CONFIG_VIDEO_HDMI || defined CONFIG_VIDEO_VGA || CONFIG_VIDEO_COMPOSITE */ @@ -999,6 +1008,8 @@ static void sunxi_tvencoder_mode_set(void) struct sunxi_tve_reg * const tve = (struct sunxi_tve_reg *)SUNXI_TVE0_BASE; + /* Reset off */ + setbits_le32(&ccm->lcd0_ch0_clk_cfg, CCM_LCD_CH0_CTRL_TVE_RST); /* Clock on */ setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_TVE0); |
