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| author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2016-05-24 21:13:57 +0900 |
|---|---|---|
| committer | Masahiro Yamada <yamada.masahiro@socionext.com> | 2016-05-26 00:35:26 +0900 |
| commit | 0bd20207ab2d874842161cab37c213310d785b24 (patch) | |
| tree | da95cd1c624176e51bd12a9b709e968afd89205f /drivers/soc/keystone | |
| parent | fc15b9beed05dec6cc092c265042381a0eadb0e9 (diff) | |
| download | talos-obmc-uboot-0bd20207ab2d874842161cab37c213310d785b24.tar.gz talos-obmc-uboot-0bd20207ab2d874842161cab37c213310d785b24.zip | |
ARM: uniphier: disable cache in SPL of PH1-LD20
The Boot ROM has enabled D-cache and MMU setting DDR memory area
as Normal Memory in its page table. Disable D-cache and MMU
before jumping to U-Boot proper.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'drivers/soc/keystone')
0 files changed, 0 insertions, 0 deletions
