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authorAkshay Saraswat <akshay.s@samsung.com>2013-03-22 02:26:36 +0000
committerMinkyu Kang <mk7.kang@samsung.com>2013-05-21 20:17:30 +0900
commit234370cab4b2f096e095fe8f3284fd39740a4023 (patch)
tree1ce12817aa13a62f65562f5b9191de5956e4a892 /drivers/serial/serial_s5p.c
parentc7c4fe072eeb95852f4a015df3c1a39b37caae51 (diff)
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Exynos5: clock: Update the equation to calculate PLL output frequency
According to the latest exynos5 user manual, the equation for calculating PLL output was changed to FOUT= MDIV x FIN/(PDIV x 2^SDIV) earlier it was FOUT= MDIV x FIN/(PDIV x 2^(SDIV -1)) So updating the clock code accordingly. Signed-off-by: Hatim Ali <hatim.rv@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Diffstat (limited to 'drivers/serial/serial_s5p.c')
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