diff options
| author | Prabhakar Kushwaha <prabhakar@freescale.com> | 2011-02-01 15:55:58 +0000 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2011-03-29 07:41:37 -0500 |
| commit | b03a466d6ceb9dbfd1a1638f355e9c8b4833259f (patch) | |
| tree | 5969f3c69be00b44b0fdf7c00c1d180d414e4b09 /drivers/pci | |
| parent | 2d7534a344412409d03e4a341614e4320c48879b (diff) | |
| download | talos-obmc-uboot-b03a466d6ceb9dbfd1a1638f355e9c8b4833259f.tar.gz talos-obmc-uboot-b03a466d6ceb9dbfd1a1638f355e9c8b4833259f.zip | |
powerpc/85xx: Handle PCIe initialization requires for P1021 class SoCs
The P1011, P1012, P1015, P1016, P1020, P1021, P1024, & P1025 SoCs require
that we initialize the SERDES registers if the lanes are configured for
PCIe. Additionally these devices PCIe controller do not support ASPM
and we have to explicitly disable it.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'drivers/pci')
| -rw-r--r-- | drivers/pci/fsl_pci_init.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 3118b85faa..dc34bd6669 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -317,6 +317,13 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) temp32 |= 0xf000e; /* set URR, FER, NFER (but not CER) */ pci_hose_write_config_dword(hose, dev, PCI_DCR, temp32); +#if defined(CONFIG_FSL_PCIE_DISABLE_ASPM) + temp32 = 0; + pci_hose_read_config_dword(hose, dev, PCI_LCR, &temp32); + temp32 &= ~0x03; /* Disable ASPM */ + pci_hose_write_config_dword(hose, dev, PCI_LCR, temp32); + udelay(1); +#endif if (pcie_cap == PCI_CAP_ID_EXP) { pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm); enabled = ltssm >= PCI_LTSSM_L0; |
