Merge branch 'next' of ../master

2 files changed, 107 insertions, 218 deletions

diff --git a/drivers/net/mpc512x_fec.c b/drivers/net/mpc512x_fec.c
index 7078c4ef77..fb2c19a71b 100644
--- a/drivers/net/mpc512x_fec.c
+++ b/drivers/net/mpc512x_fec.c
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2003-2007
+ * (C) Copyright 2003-2009
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * Derived from the MPC8xx FEC driver.
@@ -7,11 +7,11 @@
  */
 
 #include <common.h>
-#include <mpc512x.h>
 #include <malloc.h>
 #include <net.h>
 #include <netdev.h>
 #include <miiphy.h>
+#include <asm/io.h>
 #include "mpc512x_fec.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -26,11 +26,11 @@ DECLARE_GLOBAL_DATA_PTR;
 #endif
 
 #if (DEBUG & 0x40)
-static uint32 local_crc32(char *string, unsigned int crc_value, int len);
+static u32 local_crc32(char *string, unsigned int crc_value, int len);
 #endif
 
-int fec512x_miiphy_read(char *devname, uint8 phyAddr, uint8 regAddr, uint16 * retVal);
-int fec512x_miiphy_write(char *devname, uint8 phyAddr, uint8 regAddr, uint16 data);
+int fec512x_miiphy_read(char *devname, u8 phyAddr, u8 regAddr, u16 * retVal);
+int fec512x_miiphy_write(char *devname, u8 phyAddr, u8 regAddr, u16 data);
 int mpc512x_fec_init_phy(struct eth_device *dev, bd_t * bis);
 
 static uchar rx_buff[FEC_BUFFER_SIZE];
@@ -40,9 +40,9 @@ static int rx_buff_idx = 0;
 #if (DEBUG & 0x2)
 static void mpc512x_fec_phydump (char *devname)
 {
-	uint16 phyStatus, i;
-	uint8 phyAddr = CONFIG_PHY_ADDR;
-	uint8 reg_mask[] = {
+	u16 phyStatus, i;
+	u8 phyAddr = CONFIG_PHY_ADDR;
+	u8 reg_mask[] = {
 		/* regs to print: 0...8, 21,27,31 */
 		1, 1, 1, 1,  1, 1, 1, 1,     1, 0, 0, 0,  0, 0, 0, 0,
 		0, 0, 0, 0,  0, 1, 0, 0,     0, 0, 0, 1,  0, 0, 0, 1,
@@ -66,7 +66,8 @@ static int mpc512x_fec_bd_init (mpc512x_fec_priv *fec)
 	 * Receive BDs init
 	 */
 	for (ix = 0; ix < FEC_RBD_NUM; ix++) {
-		fec->bdBase->rbd[ix].dataPointer = (uint32)&fec->bdBase->recv_frames[ix];
+		fec->bdBase->rbd[ix].dataPointer =
+				(u32)&fec->bdBase->recv_frames[ix];
 		fec->bdBase->rbd[ix].status = FEC_RBD_EMPTY;
 		fec->bdBase->rbd[ix].dataLength = 0;
 	}
@@ -119,8 +120,9 @@ static void mpc512x_fec_rbd_clean (mpc512x_fec_priv *fec, volatile FEC_RBD * pRb
 
 	/*
 	 * Now, we have an empty RxBD, notify FEC
+	 * Set Descriptor polling active
 	 */
-	fec->eth->r_des_active = 0x01000000;	/* Descriptor polling active */
+	out_be32(&fec->eth->r_des_active, 0x01000000);
 }
 
 /********************************************************************/
@@ -164,10 +166,10 @@ static void mpc512x_fec_tbd_scrub (mpc512x_fec_priv *fec)
 /********************************************************************/
 static void mpc512x_fec_set_hwaddr (mpc512x_fec_priv *fec, char *mac)
 {
-	uint8 currByte;			/* byte for which to compute the CRC */
+	u8 currByte;			/* byte for which to compute the CRC */
 	int byte;			/* loop - counter */
 	int bit;			/* loop - counter */
-	uint32 crc = 0xffffffff;	/* initial value */
+	u32 crc = 0xffffffff;		/* initial value */
 
 	/*
 	 * The algorithm used is the following:
@@ -203,18 +205,20 @@ static void mpc512x_fec_set_hwaddr (mpc512x_fec_priv *fec, char *mac)
 	 * Set individual hash table register
 	 */
 	if (crc >= 32) {
-		fec->eth->iaddr1 = (1 << (crc - 32));
-		fec->eth->iaddr2 = 0;
+		out_be32(&fec->eth->iaddr1, (1 << (crc - 32)));
+		out_be32(&fec->eth->iaddr2, 0);
 	} else {
-		fec->eth->iaddr1 = 0;
-		fec->eth->iaddr2 = (1 << crc);
+		out_be32(&fec->eth->iaddr1, 0);
+		out_be32(&fec->eth->iaddr2, (1 << crc));
 	}
 
 	/*
 	 * Set physical address
 	 */
-	fec->eth->paddr1 = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3];
-	fec->eth->paddr2 = (mac[4] << 24) + (mac[5] << 16) + 0x8808;
+	out_be32(&fec->eth->paddr1, (mac[0] << 24) + (mac[1] << 16) +
+				    (mac[2] <<  8) + mac[3]);
+	out_be32(&fec->eth->paddr2, (mac[4] << 24) + (mac[5] << 16) +
+				     0x8808);
 }
 
 /********************************************************************/
@@ -227,45 +231,45 @@ static int mpc512x_fec_init (struct eth_device *dev, bd_t * bis)
 #endif
 
 	/* Set interrupt mask register */
-	fec->eth->imask = 0x00000000;
+	out_be32(&fec->eth->imask, 0x00000000);
 
 	/* Clear FEC-Lite interrupt event register(IEVENT) */
-	fec->eth->ievent = 0xffffffff;
+	out_be32(&fec->eth->ievent, 0xffffffff);
 
 	/* Set transmit fifo watermark register(X_WMRK), default = 64 */
-	fec->eth->x_wmrk = 0x0;
+	out_be32(&fec->eth->x_wmrk, 0x0);
 
 	/* Set Opcode/Pause Duration Register */
-	fec->eth->op_pause = 0x00010020;
+	out_be32(&fec->eth->op_pause, 0x00010020);
 
 	/* Frame length=1522; MII mode */
-	fec->eth->r_cntrl = (FEC_MAX_FRAME_LEN << 16) | 0x24;
+	out_be32(&fec->eth->r_cntrl, (FEC_MAX_FRAME_LEN << 16) | 0x24);
 
 	/* Half-duplex, heartbeat disabled */
-	fec->eth->x_cntrl = 0x00000000;
+	out_be32(&fec->eth->x_cntrl, 0x00000000);
 
 	/* Enable MIB counters */
-	fec->eth->mib_control = 0x0;
+	out_be32(&fec->eth->mib_control, 0x0);
 
 	/* Setup recv fifo start and buff size */
-	fec->eth->r_fstart = 0x500;
-	fec->eth->r_buff_size = FEC_BUFFER_SIZE;
+	out_be32(&fec->eth->r_fstart, 0x500);
+	out_be32(&fec->eth->r_buff_size, FEC_BUFFER_SIZE);
 
 	/* Setup BD base addresses */
-	fec->eth->r_des_start = (uint32)fec->bdBase->rbd;
-	fec->eth->x_des_start = (uint32)fec->bdBase->tbd;
+	out_be32(&fec->eth->r_des_start, (u32)fec->bdBase->rbd);
+	out_be32(&fec->eth->x_des_start, (u32)fec->bdBase->tbd);
 
 	/* DMA Control */
-	fec->eth->dma_control = 0xc0000000;
+	out_be32(&fec->eth->dma_control, 0xc0000000);
 
 	/* Enable FEC */
-	fec->eth->ecntrl |= 0x00000006;
+	setbits_be32(&fec->eth->ecntrl, 0x00000006);
 
 	/* Initilize addresses and status words of BDs */
 	mpc512x_fec_bd_init (fec);
 
 	 /* Descriptor polling active */
-	fec->eth->r_des_active = 0x01000000;
+	out_be32(&fec->eth->r_des_active, 0x01000000);
 
 #if (DEBUG & 0x1)
 	printf("mpc512x_fec_init... Done \n");
@@ -277,9 +281,9 @@ static int mpc512x_fec_init (struct eth_device *dev, bd_t * bis)
 int mpc512x_fec_init_phy (struct eth_device *dev, bd_t * bis)
 {
 	mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv;
-	const uint8 phyAddr = CONFIG_PHY_ADDR;	/* Only one PHY */
+	const u8 phyAddr = CONFIG_PHY_ADDR;	/* Only one PHY */
 	int timeout = 1;
-	uint16 phyStatus;
+	u16 phyStatus;
 
 #if (DEBUG & 0x1)
 	printf ("mpc512x_fec_init_phy... Begin\n");
@@ -288,19 +292,20 @@ int mpc512x_fec_init_phy (struct eth_device *dev, bd_t * bis)
 	/*
 	 * Clear FEC-Lite interrupt event register(IEVENT)
 	 */
-	fec->eth->ievent = 0xffffffff;
+	out_be32(&fec->eth->ievent, 0xffffffff);
 
 	/*
 	 * Set interrupt mask register
 	 */
-	fec->eth->imask = 0x00000000;
+	out_be32(&fec->eth->imask, 0x00000000);
 
 	if (fec->xcv_type != SEVENWIRE) {
 		/*
 		 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
 		 * and do not drop the Preamble.
 		 */
-		fec->eth->mii_speed = (((gd->ips_clk / 1000000) / 5) + 1) << 1;
+		out_be32(&fec->eth->mii_speed,
+			 (((gd->ips_clk / 1000000) / 5) + 1) << 1);
 
 		/*
 		 * Reset PHY, then delay 300ns
@@ -414,27 +419,28 @@ static void mpc512x_fec_halt (struct eth_device *dev)
 	/*
 	 * mask FEC chip interrupts
 	 */
-	fec->eth->imask = 0;
+	out_be32(&fec->eth->imask, 0);
 
 	/*
 	 * issue graceful stop command to the FEC transmitter if necessary
 	 */
-	fec->eth->x_cntrl |= 0x00000001;
+	setbits_be32(&fec->eth->x_cntrl, 0x00000001);
 
 	/*
 	 * wait for graceful stop to register
 	 */
-	while ((counter--) && (!(fec->eth->ievent & 0x10000000))) ;
+	while ((counter--) && (!(in_be32(&fec->eth->ievent) & 0x10000000)))
+		;
 
 	/*
 	 * Disable the Ethernet Controller
 	 */
-	fec->eth->ecntrl &= 0xfffffffd;
+	clrbits_be32(&fec->eth->ecntrl, 0x00000002);
 
 	/*
 	 * Issue a reset command to the FEC chip
 	 */
-	fec->eth->ecntrl |= 0x1;
+	setbits_be32(&fec->eth->ecntrl, 0x1);
 
 	/*
 	 * wait at least 16 clock cycles
@@ -488,12 +494,12 @@ static int mpc512x_fec_send (struct eth_device *dev, volatile void *eth_data,
 	 */
 	pTbd = &fec->bdBase->tbd[fec->tbdIndex];
 	pTbd->dataLength = data_length;
-	pTbd->dataPointer = (uint32)eth_data;
+	pTbd->dataPointer = (u32)eth_data;
 	pTbd->status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
 	fec->tbdIndex = (fec->tbdIndex + 1) % FEC_TBD_NUM;
 
 	/* Activate transmit Buffer Descriptor polling */
-	fec->eth->x_des_active = 0x01000000;	/* Descriptor polling active	*/
+	out_be32(&fec->eth->x_des_active, 0x01000000);
 
 #if (DEBUG & 0x8)
 	printf ( "+" );
@@ -536,8 +542,8 @@ static int mpc512x_fec_recv (struct eth_device *dev)
 	/*
 	 * Check if any critical events have happened
 	 */
-	ievent = fec->eth->ievent;
-	fec->eth->ievent = ievent;
+	ievent = in_be32(&fec->eth->ievent);
+	out_be32(&fec->eth->ievent, ievent);
 	if (ievent & 0x20060000) {
 		/* BABT, Rx/Tx FIFO errors */
 		mpc512x_fec_halt (dev);
@@ -546,13 +552,13 @@ static int mpc512x_fec_recv (struct eth_device *dev)
 	}
 	if (ievent & 0x80000000) {
 		/* Heartbeat error */
-		fec->eth->x_cntrl |= 0x00000001;
+		setbits_be32(&fec->eth->x_cntrl, 0x00000001);
 	}
 	if (ievent & 0x10000000) {
 		/* Graceful stop complete */
-		if (fec->eth->x_cntrl & 0x00000001) {
+		if (in_be32(&fec->eth->x_cntrl) & 0x00000001) {
 			mpc512x_fec_halt (dev);
-			fec->eth->x_cntrl &= ~0x00000001;
+			clrbits_be32(&fec->eth->x_cntrl, 0x00000001);;
 			mpc512x_fec_init (dev, NULL);
 		}
 	}
@@ -574,7 +580,7 @@ static int mpc512x_fec_recv (struct eth_device *dev)
 				printf ("recv data length 0x%08x data hdr: ",
 					pRbd->dataLength);
 				for (i = 0; i < 14; i++)
-					printf ("%x ", *((uint8*)pRbd->dataPointer + i));
+					printf ("%x ", *((u8*)pRbd->dataPointer + i));
 				printf("\n");
 			}
 #endif
@@ -598,13 +604,15 @@ static int mpc512x_fec_recv (struct eth_device *dev)
 	}
 
 	/* Try to fill Buffer Descriptors */
-	fec->eth->r_des_active = 0x01000000;	/* Descriptor polling active */
+	out_be32(&fec->eth->r_des_active, 0x01000000);
+
 	return frame_length;
 }
 
 /********************************************************************/
 int mpc512x_fec_initialize (bd_t * bis)
 {
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 	mpc512x_fec_priv *fec;
 	struct eth_device *dev;
 	int i;
@@ -615,7 +623,7 @@ int mpc512x_fec_initialize (bd_t * bis)
 	dev = (struct eth_device *) malloc (sizeof(*dev));
 	memset (dev, 0, sizeof *dev);
 
-	fec->eth = (ethernet_regs *) MPC512X_FEC;
+	fec->eth = &im->fec;
 
 # ifndef CONFIG_FEC_10MBIT
 	fec->xcv_type = MII100;
@@ -623,7 +631,7 @@ int mpc512x_fec_initialize (bd_t * bis)
 	fec->xcv_type = MII10;
 # endif
 	dev->priv = (void *)fec;
-	dev->iobase = MPC512X_FEC;
+	dev->iobase = (int)&im->fec;
 	dev->init = mpc512x_fec_init;
 	dev->halt = mpc512x_fec_halt;
 	dev->send = mpc512x_fec_send;
@@ -638,25 +646,26 @@ int mpc512x_fec_initialize (bd_t * bis)
 #endif
 
 	/* Clean up space FEC's MIB and FIFO RAM ...*/
-	memset ((void *) MPC512X_FEC + 0x200, 0x00, 0x400);
+	memset ((void *)&im->fec.mib,  0x00, sizeof(im->fec.mib));
+	memset ((void *)&im->fec.fifo, 0x00, sizeof(im->fec.fifo));
 
 	/*
 	 * Malloc space for BDs  (must be quad word-aligned)
 	 * this pointer is lost, so cannot be freed
 	 */
 	bd = malloc (sizeof(mpc512x_buff_descs) + 0x1f);
-	fec->bdBase = (mpc512x_buff_descs*)((uint32)bd & 0xfffffff0);
+	fec->bdBase = (mpc512x_buff_descs*)((u32)bd & 0xfffffff0);
 	memset ((void *) bd, 0x00, sizeof(mpc512x_buff_descs) + 0x1f);
 
 	/*
 	 * Set interrupt mask register
 	 */
-	fec->eth->imask = 0x00000000;
+	out_be32(&fec->eth->imask, 0x00000000);
 
 	/*
 	 * Clear FEC-Lite interrupt event register(IEVENT)
 	 */
-	fec->eth->ievent = 0xffffffff;
+	out_be32(&fec->eth->ievent, 0xffffffff);
 
 	/*
 	 * Try to set the mac address now. The fec mac address is
@@ -671,8 +680,8 @@ int mpc512x_fec_initialize (bd_t * bis)
 				tmp = (*end) ? end+1 : end;
 		}
 		mpc512x_fec_set_hwaddr (fec, env_enetaddr);
-		fec->eth->gaddr1 = 0x00000000;
-		fec->eth->gaddr2 = 0x00000000;
+		out_be32(&fec->eth->gaddr1, 0x00000000);
+		out_be32(&fec->eth->gaddr2, 0x00000000);
 	}
 
 	mpc512x_fec_init_phy (dev, bis);
@@ -682,11 +691,12 @@ int mpc512x_fec_initialize (bd_t * bis)
 
 /* MII-interface related functions */
 /********************************************************************/
-int fec512x_miiphy_read (char *devname, uint8 phyAddr, uint8 regAddr, uint16 * retVal)
+int fec512x_miiphy_read (char *devname, u8 phyAddr, u8 regAddr, u16 * retVal)
 {
-	ethernet_regs *eth = (ethernet_regs *) MPC512X_FEC;
-	uint32 reg;		/* convenient holder for the PHY register */
-	uint32 phy;		/* convenient holder for the PHY */
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	volatile fec512x_t *eth = &im->fec;
+	u32 reg;		/* convenient holder for the PHY register */
+	u32 phy;		/* convenient holder for the PHY */
 	int timeout = 0xffff;
 
 	/*
@@ -696,12 +706,16 @@ int fec512x_miiphy_read (char *devname, uint8 phyAddr, uint8 regAddr, uint16 * r
 	reg = regAddr << FEC_MII_DATA_RA_SHIFT;
 	phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
 
-	eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | phy | reg);
+	out_be32(&eth->mii_data, FEC_MII_DATA_ST |
+				 FEC_MII_DATA_OP_RD |
+				 FEC_MII_DATA_TA |
+				 phy | reg);
 
 	/*
 	 * wait for the related interrupt
 	 */
-	while ((timeout--) && (!(eth->ievent & 0x00800000))) ;
+	while ((timeout--) && (!(in_be32(&eth->ievent) & 0x00800000)))
+		;
 
 	if (timeout == 0) {
 #if (DEBUG & 0x2)
@@ -713,34 +727,38 @@ int fec512x_miiphy_read (char *devname, uint8 phyAddr, uint8 regAddr, uint16 * r
 	/*
 	 * clear mii interrupt bit
 	 */
-	eth->ievent = 0x00800000;
+	out_be32(&eth->ievent, 0x00800000);
 
 	/*
 	 * it's now safe to read the PHY's register
 	 */
-	*retVal = (uint16) eth->mii_data;
+	*retVal = (u16) in_be32(&eth->mii_data);
 
 	return 0;
 }
 
 /********************************************************************/
-int fec512x_miiphy_write (char *devname, uint8 phyAddr, uint8 regAddr, uint16 data)
+int fec512x_miiphy_write (char *devname, u8 phyAddr, u8 regAddr, u16 data)
 {
-	ethernet_regs *eth = (ethernet_regs *) MPC512X_FEC;
-	uint32 reg;		/* convenient holder for the PHY register */
-	uint32 phy;		/* convenient holder for the PHY */
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	volatile fec512x_t *eth = &im->fec;
+	u32 reg;		/* convenient holder for the PHY register */
+	u32 phy;		/* convenient holder for the PHY */
 	int timeout = 0xffff;
 
 	reg = regAddr << FEC_MII_DATA_RA_SHIFT;
 	phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
 
-	eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
-			FEC_MII_DATA_TA | phy | reg | data);
+	out_be32(&eth->mii_data, FEC_MII_DATA_ST |
+				 FEC_MII_DATA_OP_WR |
+				 FEC_MII_DATA_TA |
+				 phy | reg | data);
 
 	/*
 	 * wait for the MII interrupt
 	 */
-	while ((timeout--) && (!(eth->ievent & 0x00800000))) ;
+	while ((timeout--) && (!(in_be32(&eth->ievent) & 0x00800000)))
+		;
 
 	if (timeout == 0) {
 #if (DEBUG & 0x2)
@@ -752,13 +770,13 @@ int fec512x_miiphy_write (char *devname, uint8 phyAddr, uint8 regAddr, uint16 da
 	/*
 	 * clear MII interrupt bit
 	 */
-	eth->ievent = 0x00800000;
+	out_be32(&eth->ievent, 0x00800000);
 
 	return 0;
 }
 
 #if (DEBUG & 0x40)
-static uint32 local_crc32 (char *string, unsigned int crc_value, int len)
+static u32 local_crc32 (char *string, unsigned int crc_value, int len)
 {
 	int i;
 	char c;
diff --git a/drivers/net/mpc512x_fec.h b/drivers/net/mpc512x_fec.h
index 9c38502870..a083cca2f8 100644
--- a/drivers/net/mpc512x_fec.h
+++ b/drivers/net/mpc512x_fec.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2003 - 2007
+ * (C) Copyright 2003 - 2009
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * Derived from the MPC8xx driver's header file.
@@ -9,147 +9,18 @@
 #define __MPC512X_FEC_H
 
 #include <common.h>
-#include <mpc512x.h>
-
-typedef unsigned long uint32;
-typedef unsigned short uint16;
-typedef unsigned char uint8;
-
-typedef struct ethernet_register_set {
-
-/* [10:2]addr = 00 */
-
-/*  Control and status Registers (offset 000-1FF) */
-
-	volatile uint32 fec_id;			/* MBAR_ETH + 0x000 */
-	volatile uint32 ievent;			/* MBAR_ETH + 0x004 */
-	volatile uint32 imask;			/* MBAR_ETH + 0x008 */
-
-	volatile uint32 RES0[1];		/* MBAR_ETH + 0x00C */
-	volatile uint32 r_des_active;		/* MBAR_ETH + 0x010 */
-	volatile uint32 x_des_active;		/* MBAR_ETH + 0x014 */
-
-	volatile uint32 RES1[3];		/* MBAR_ETH + 0x018-020 */
-	volatile uint32 ecntrl;			/* MBAR_ETH + 0x024 */
-
-	volatile uint32 RES2[6];		/* MBAR_ETH + 0x028-03C */
-	volatile uint32 mii_data;		/* MBAR_ETH + 0x040 */
-	volatile uint32 mii_speed;		/* MBAR_ETH + 0x044 */
-
-	volatile uint32 RES3[7];		/* MBAR_ETH + 0x048-060 */
-	volatile uint32 mib_control;		/* MBAR_ETH + 0x064 */
-
-	volatile uint32 RES4[7];		/* MBAR_ETH + 0x068-80 */
-	volatile uint32 r_cntrl;		/* MBAR_ETH + 0x084 */
-	volatile uint32 r_hash;			/* MBAR_ETH + 0x088 */
-
-	volatile uint32 RES5[14];		/* MBAR_ETH + 0x08c-0C0 */
-	volatile uint32 x_cntrl;		/* MBAR_ETH + 0x0C4 */
-
-	volatile uint32 RES6[7];		/* MBAR_ETH + 0x0C8-0E0 */
-	volatile uint32 paddr1;			/* MBAR_ETH + 0x0E4 */
-	volatile uint32 paddr2;			/* MBAR_ETH + 0x0E8 */
-	volatile uint32 op_pause;		/* MBAR_ETH + 0x0EC */
-
-	volatile uint32 RES7[10];		/* MBAR_ETH + 0x0F0-114 */
-	volatile uint32 iaddr1;			/* MBAR_ETH + 0x118 */
-	volatile uint32 iaddr2;			/* MBAR_ETH + 0x11C */
-	volatile uint32 gaddr1;			/* MBAR_ETH + 0x120 */
-	volatile uint32 gaddr2;			/* MBAR_ETH + 0x124 */
-
-	volatile uint32 RES8[6];		/* MBAR_ETH + 0x128-13C */
-	volatile uint32 fifo_id;		/* MBAR_ETH + 0x140 */
-	volatile uint32 x_wmrk;			/* MBAR_ETH + 0x144 */
-	volatile uint32 RES9[1];		/* MBAR_ETH + 0x148 */
-	volatile uint32 r_bound;		/* MBAR_ETH + 0x14C */
-	volatile uint32 r_fstart;		/* MBAR_ETH + 0x150 */
-
-	volatile uint32 RES10[11];		/* MBAR_ETH + 0x154-17C */
-	volatile uint32 r_des_start;		/* MBAR_ETH + 0x180 */
-	volatile uint32 x_des_start;		/* MBAR_ETH + 0x184 */
-	volatile uint32 r_buff_size;		/* MBAR_ETH + 0x188 */
-	volatile uint32 RES11[26];		/* MBAR_ETH + 0x18C-1F0 */
-	volatile uint32 dma_control;		/* MBAR_ETH + 0x1F4 */
-	volatile uint32 RES12[2];		/* MBAR_ETH + 0x1F8-1FC */
-
-/*  MIB COUNTERS (Offset 200-2FF) */
-
-	volatile uint32 rmon_t_drop;		/* MBAR_ETH + 0x200 */
-	volatile uint32 rmon_t_packets;		/* MBAR_ETH + 0x204 */
-	volatile uint32 rmon_t_bc_pkt;		/* MBAR_ETH + 0x208 */
-	volatile uint32 rmon_t_mc_pkt;		/* MBAR_ETH + 0x20C */
-	volatile uint32 rmon_t_crc_align;	/* MBAR_ETH + 0x210 */
-	volatile uint32 rmon_t_undersize;	/* MBAR_ETH + 0x214 */
-	volatile uint32 rmon_t_oversize;	/* MBAR_ETH + 0x218 */
-	volatile uint32 rmon_t_frag;		/* MBAR_ETH + 0x21C */
-	volatile uint32 rmon_t_jab;		/* MBAR_ETH + 0x220 */
-	volatile uint32 rmon_t_col;		/* MBAR_ETH + 0x224 */
-	volatile uint32 rmon_t_p64;		/* MBAR_ETH + 0x228 */
-	volatile uint32 rmon_t_p65to127;	/* MBAR_ETH + 0x22C */
-	volatile uint32 rmon_t_p128to255;	/* MBAR_ETH + 0x230 */
-	volatile uint32 rmon_t_p256to511;	/* MBAR_ETH + 0x234 */
-	volatile uint32 rmon_t_p512to1023;	/* MBAR_ETH + 0x238 */
-	volatile uint32 rmon_t_p1024to2047;	/* MBAR_ETH + 0x23C */
-	volatile uint32 rmon_t_p_gte2048;	/* MBAR_ETH + 0x240 */
-	volatile uint32 rmon_t_octets;		/* MBAR_ETH + 0x244 */
-	volatile uint32 ieee_t_drop;		/* MBAR_ETH + 0x248 */
-	volatile uint32 ieee_t_frame_ok;	/* MBAR_ETH + 0x24C */
-	volatile uint32 ieee_t_1col;		/* MBAR_ETH + 0x250 */
-	volatile uint32 ieee_t_mcol;		/* MBAR_ETH + 0x254 */
-	volatile uint32 ieee_t_def;		/* MBAR_ETH + 0x258 */
-	volatile uint32 ieee_t_lcol;		/* MBAR_ETH + 0x25C */
-	volatile uint32 ieee_t_excol;		/* MBAR_ETH + 0x260 */
-	volatile uint32 ieee_t_macerr;		/* MBAR_ETH + 0x264 */
-	volatile uint32 ieee_t_cserr;		/* MBAR_ETH + 0x268 */
-	volatile uint32 ieee_t_sqe;		/* MBAR_ETH + 0x26C */
-	volatile uint32 t_fdxfc;		/* MBAR_ETH + 0x270 */
-	volatile uint32 ieee_t_octets_ok;	/* MBAR_ETH + 0x274 */
-
-	volatile uint32 RES13[2];		/* MBAR_ETH + 0x278-27C */
-	volatile uint32 rmon_r_drop;		/* MBAR_ETH + 0x280 */
-	volatile uint32 rmon_r_packets;		/* MBAR_ETH + 0x284 */
-	volatile uint32 rmon_r_bc_pkt;		/* MBAR_ETH + 0x288 */
-	volatile uint32 rmon_r_mc_pkt;		/* MBAR_ETH + 0x28C */
-	volatile uint32 rmon_r_crc_align;	/* MBAR_ETH + 0x290 */
-	volatile uint32 rmon_r_undersize;	/* MBAR_ETH + 0x294 */
-	volatile uint32 rmon_r_oversize;	/* MBAR_ETH + 0x298 */
-	volatile uint32 rmon_r_frag;		/* MBAR_ETH + 0x29C */
-	volatile uint32 rmon_r_jab;		/* MBAR_ETH + 0x2A0 */
-
-	volatile uint32 rmon_r_resvd_0;		/* MBAR_ETH + 0x2A4 */
-
-	volatile uint32 rmon_r_p64;		/* MBAR_ETH + 0x2A8 */
-	volatile uint32 rmon_r_p65to127;	/* MBAR_ETH + 0x2AC */
-	volatile uint32 rmon_r_p128to255;	/* MBAR_ETH + 0x2B0 */
-	volatile uint32 rmon_r_p256to511;	/* MBAR_ETH + 0x2B4 */
-	volatile uint32 rmon_r_p512to1023;	/* MBAR_ETH + 0x2B8 */
-	volatile uint32 rmon_r_p1024to2047;	/* MBAR_ETH + 0x2BC */
-	volatile uint32 rmon_r_p_gte2048;	/* MBAR_ETH + 0x2C0 */
-	volatile uint32 rmon_r_octets;		/* MBAR_ETH + 0x2C4 */
-	volatile uint32 ieee_r_drop;		/* MBAR_ETH + 0x2C8 */
-	volatile uint32 ieee_r_frame_ok;	/* MBAR_ETH + 0x2CC */
-	volatile uint32 ieee_r_crc;		/* MBAR_ETH + 0x2D0 */
-	volatile uint32 ieee_r_align;		/* MBAR_ETH + 0x2D4 */
-	volatile uint32 r_macerr;		/* MBAR_ETH + 0x2D8 */
-	volatile uint32 r_fdxfc;		/* MBAR_ETH + 0x2DC */
-	volatile uint32 ieee_r_octets_ok;	/* MBAR_ETH + 0x2E0 */
-
-	volatile uint32 RES14[6];		/* MBAR_ETH + 0x2E4-2FC */
-
-	volatile uint32 RES15[64];		/* MBAR_ETH + 0x300-3FF */
-} ethernet_regs;
 
 /* Receive & Transmit Buffer Descriptor definitions */
 typedef struct BufferDescriptor {
-	uint16 status;
-	uint16 dataLength;
-	uint32 dataPointer;
+	u16 status;
+	u16 dataLength;
+	u32 dataPointer;
 } FEC_RBD;
 
 typedef struct {
-	uint16 status;
-	uint16 dataLength;
-	uint32 dataPointer;
+	u16 status;
+	u16 dataLength;
+	u32 dataPointer;
 } FEC_TBD;
 
 /* private structure */
@@ -170,7 +41,7 @@ typedef enum {
 #define FEC_BUFFER_SIZE		((FEC_MAX_FRAME_LEN + 0x10) & (~0xf))
 
 typedef struct {
-	uint8 frame[FEC_BUFFER_SIZE];
+	u8 frame[FEC_BUFFER_SIZE];
 } mpc512x_frame;
 
 typedef struct {
@@ -180,13 +51,13 @@ typedef struct {
 } mpc512x_buff_descs;
 
 typedef struct {
-	ethernet_regs *eth;
+	volatile fec512x_t *eth;
 	xceiver_type xcv_type;		/* transceiver type */
 	mpc512x_buff_descs *bdBase;	/* BD rings and recv buffer */
-	uint16 rbdIndex;		/* next receive BD to read */
-	uint16 tbdIndex;		/* next transmit BD to send */
-	uint16 usedTbdIndex;		/* next transmit BD to clean */
-	uint16 cleanTbdNum;		/* the number of available transmit BDs */
+	u16 rbdIndex;			/* next receive BD to read */
+	u16 tbdIndex;			/* next transmit BD to send */
+	u16 usedTbdIndex;		/* next transmit BD to clean */
+	u16 cleanTbdNum;		/* the number of available transmit BDs */
 } mpc512x_fec_priv;
 
 /* RBD bits definitions */