diff options
| author | Soren Brinkmann <soren.brinkmann@xilinx.com> | 2013-11-21 13:39:00 -0800 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2014-02-19 09:41:21 +0100 |
| commit | 1cd46ed2d30a931a66400635f158b14861f2d3b4 (patch) | |
| tree | ee03e2c758c81e0cb325a8afb3b0db2779950600 /drivers/net | |
| parent | 2826fd320cf364077ccc64e645af468adcbe567e (diff) | |
| download | talos-obmc-uboot-1cd46ed2d30a931a66400635f158b14861f2d3b4.tar.gz talos-obmc-uboot-1cd46ed2d30a931a66400635f158b14861f2d3b4.zip | |
net: zynq_gem: Move RCLK details out of driver
The GEM driver should not need to know about Zynq specific details of
RCLK related registers and bitfields in the SLCR. Move those details to
the slcr driver.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'drivers/net')
| -rw-r--r-- | drivers/net/zynq_gem.c | 7 |
1 files changed, 2 insertions, 5 deletions
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 381bca459e..2eb9e7d1ef 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -270,7 +270,7 @@ static int zynq_gem_setup_mac(struct eth_device *dev) static int zynq_gem_init(struct eth_device *dev, bd_t * bis) { - u32 i, rclk, clk = 0; + u32 i, clk = 0; struct phy_device *phydev; const u32 stat_size = (sizeof(struct zynq_gem_regs) - offsetof(struct zynq_gem_regs, stat)) / 4; @@ -348,17 +348,14 @@ static int zynq_gem_init(struct eth_device *dev, bd_t * bis) case SPEED_1000: writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED1000, ®s->nwcfg); - rclk = (0 << 4) | (1 << 0); clk = (1 << 20) | (8 << 8) | (0 << 4) | (1 << 0); break; case SPEED_100: clrsetbits_le32(®s->nwcfg, ZYNQ_GEM_NWCFG_SPEED1000, ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED100); - rclk = 1 << 0; clk = (5 << 20) | (8 << 8) | (0 << 4) | (1 << 0); break; case SPEED_10: - rclk = 1 << 0; /* FIXME untested */ clk = (5 << 20) | (8 << 8) | (0 << 4) | (1 << 0); break; @@ -367,7 +364,7 @@ static int zynq_gem_init(struct eth_device *dev, bd_t * bis) /* Change the rclk and clk only not using EMIO interface */ if (!priv->emio) zynq_slcr_gem_clk_setup(dev->iobase != - ZYNQ_GEM_BASEADDR0, rclk, clk); + ZYNQ_GEM_BASEADDR0, clk); setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | ZYNQ_GEM_NWCTRL_TXEN_MASK); |
