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| author | Prabhakar Kushwaha <prabhakar@freescale.com> | 2014-06-14 08:48:19 +0530 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2014-07-22 16:25:54 -0700 |
| commit | 591dd192307d81cf8f8705b06854e973c53d4c4d (patch) | |
| tree | 38b6eb8c5b11734a57cee2a1a273073eb8aa0106 /drivers/mtd/nand | |
| parent | 32514d259bf37cc92872aeb0624b75f600e7fb3a (diff) | |
| download | talos-obmc-uboot-591dd192307d81cf8f8705b06854e973c53d4c4d.tar.gz talos-obmc-uboot-591dd192307d81cf8f8705b06854e973c53d4c4d.zip | |
driver/nand: Add support of 16K SRAM for IFC 2.0
Internal SRAM has been incresed from 8KB to 16KB for IFC cotroller ver 2.0.
Update the page offset calculation logic to support the same.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'drivers/mtd/nand')
| -rw-r--r-- | drivers/mtd/nand/fsl_ifc_nand.c | 4 | ||||
| -rw-r--r-- | drivers/mtd/nand/fsl_ifc_spl.c | 6 |
2 files changed, 8 insertions, 2 deletions
diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c index 280e14e24a..8b453cb383 100644 --- a/drivers/mtd/nand/fsl_ifc_nand.c +++ b/drivers/mtd/nand/fsl_ifc_nand.c @@ -23,7 +23,6 @@ #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 #endif -#define FSL_IFC_V1_1_0 0x01010000 #define MAX_BANKS CONFIG_SYS_FSL_IFC_BANK_COUNT #define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */ @@ -1040,6 +1039,9 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr) if (ret) return ret; + if (ver >= FSL_IFC_V2_0_0) + priv->bufnum_mask = (priv->bufnum_mask * 2) + 1; + ret = nand_scan_ident(mtd, 1, NULL); if (ret) return ret; diff --git a/drivers/mtd/nand/fsl_ifc_spl.c b/drivers/mtd/nand/fsl_ifc_spl.c index 510077282c..e336cb1c94 100644 --- a/drivers/mtd/nand/fsl_ifc_spl.c +++ b/drivers/mtd/nand/fsl_ifc_spl.c @@ -97,7 +97,7 @@ int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst) int pages_per_blk; int blk_size; int bad_marker = 0; - int bufnum_mask, bufnum; + int bufnum_mask, bufnum, ver = 0; int csor, cspr; int pos = 0; @@ -130,6 +130,10 @@ int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst) bad_marker = 5; } + ver = ifc_in32(&ifc->ifc_rev); + if (ver >= FSL_IFC_V2_0_0) + bufnum_mask = (bufnum_mask * 2) + 1; + pages_per_blk = 32 << ((csor & CSOR_NAND_PB_MASK) >> CSOR_NAND_PB_SHIFT); |
