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| author | York Sun <yorksun@freescale.com> | 2015-03-19 09:30:26 -0700 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2015-04-23 08:55:53 -0700 |
| commit | 66869f955417b89dbf6b7cbb72738b2205a26bf8 (patch) | |
| tree | 669eca4ca7d0e4d6d62ce480455d346f2b192f2f /drivers/ddr/fsl/main.c | |
| parent | f8cb101e1e3f5ee2007b78b6b12e24120385aeac (diff) | |
| download | talos-obmc-uboot-66869f955417b89dbf6b7cbb72738b2205a26bf8.tar.gz talos-obmc-uboot-66869f955417b89dbf6b7cbb72738b2205a26bf8.zip | |
drivers/ddr/fsl: Update DDR driver for DDR4
Add/update registers for DDR4, including DQ mappings. Allow raw timing
method used for all controllers. Update mode_9 register to 0x500 for
improved stability. Check DDR controller version number individually
in case a SoC has multiple DDR controllers of different versions.
Increase read-write turnaround for DDR4 high speeds.
Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'drivers/ddr/fsl/main.c')
| -rw-r--r-- | drivers/ddr/fsl/main.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c index b72b24290e..fa223834f2 100644 --- a/drivers/ddr/fsl/main.c +++ b/drivers/ddr/fsl/main.c @@ -453,7 +453,7 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, retval = compute_dimm_parameters( i, spd, pdimm, j); #ifdef CONFIG_SYS_DDR_RAW_TIMING - if (!i && !j && retval) { + if (!j && retval) { printf("SPD error on controller %d! " "Trying fallback to raw timing " "calculation\n", i); |
