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authorYork Sun <yorksun@freescale.com>2015-01-06 13:18:50 -0800
committerYork Sun <yorksun@freescale.com>2015-02-24 13:09:18 -0800
commit03e664d8f4065010ccb6c75648192200a832fd8b (patch)
treef0398fdcdc87e12da79a82cde310b1a11937641a /drivers/ddr/fsl/fsl_ddr_gen4.c
parentb87e6f88e9218da3de371bb6cc8a34924153178e (diff)
downloadtalos-obmc-uboot-03e664d8f4065010ccb6c75648192200a832fd8b.tar.gz
talos-obmc-uboot-03e664d8f4065010ccb6c75648192200a832fd8b.zip
driver/ddr/fsl: Add support for multiple DDR clocks
Controller number is passed for function calls to support individual DDR clock, depending on SoC implementation. It is backward compatible with exising platforms. Multiple clocks have been verifyed on LS2085A emulator. Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'drivers/ddr/fsl/fsl_ddr_gen4.c')
-rw-r--r--drivers/ddr/fsl/fsl_ddr_gen4.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c
index 9cca4a06dd..d9fce7d2f3 100644
--- a/drivers/ddr/fsl/fsl_ddr_gen4.c
+++ b/drivers/ddr/fsl/fsl_ddr_gen4.c
@@ -287,7 +287,7 @@ step2:
bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK)
>> SDRAM_CFG_DBW_SHIFT);
timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
- (get_ddr_freq(0) >> 20)) << 2;
+ (get_ddr_freq(ctrl_num) >> 20)) << 2;
total_gb_size_per_controller >>= 4; /* shift down to gb size */
debug("total %d GB\n", total_gb_size_per_controller);
debug("Need to wait up to %d * 10ms\n", timeout);
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