linux/kernel.h: sync min, max, min3, max3 macros with Linux

U-Boot has never cared about the type when we get max/min of two
values, but Linux Kernel does.  This commit gets min, max, min3, max3
macros synced with the kernel introducing type checks.

Many of references of those macros must be fixed to suppress warnings.
We have two options:
 - Use min, max, min3, max3 only when the arguments have the same type
   (or add casts to the arguments)
 - Use min_t/max_t instead with the appropriate type for the first
   argument

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Pavel Machek <pavel@denx.de>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
[trini: Fixup arch/blackfin/lib/string.c]
Signed-off-by: Tom Rini <trini@ti.com>

1 files changed, 11 insertions, 11 deletions

diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index 9a156bfd5e..9e2a4d2f46 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -303,7 +303,7 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
 
 #ifdef CONFIG_SYS_FSL_DDR4
 	/* tXP=max(4nCK, 6ns) */
-	int txp = max(mclk_ps * 4, 6000); /* unit=ps */
+	int txp = max((int)mclk_ps * 4, 6000); /* unit=ps */
 	trwt_mclk = 2;
 	twrt_mclk = 1;
 	act_pd_exit_mclk = picos_to_mclk(txp);
@@ -312,7 +312,7 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
 	 * MRS_CYC = max(tMRD, tMOD)
 	 * tMRD = 8nCK, tMOD = max(24nCK, 15ns)
 	 */
-	tmrd_mclk = max(24, picos_to_mclk(15000));
+	tmrd_mclk = max(24U, picos_to_mclk(15000));
 #elif defined(CONFIG_SYS_FSL_DDR3)
 	unsigned int data_rate = get_ddr_freq(0);
 	int txp;
@@ -325,7 +325,7 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
 	 * spec has not the tAXPD, we use
 	 * tAXPD=1, need design to confirm.
 	 */
-	txp = max(mclk_ps * 3, (mclk_ps > 1540 ? 7500 : 6000));
+	txp = max((int)mclk_ps * 3, (mclk_ps > 1540 ? 7500 : 6000));
 
 	tmrd_mclk = 4;
 	/* set the turnaround time */
@@ -511,8 +511,8 @@ static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
 #ifdef CONFIG_SYS_FSL_DDR4
 	refrec_ctrl = picos_to_mclk(common_dimm->trfc1_ps) - 8;
 	wrrec_mclk = picos_to_mclk(common_dimm->twr_ps);
-	acttoact_mclk = max(picos_to_mclk(common_dimm->trrds_ps), 4);
-	wrtord_mclk = max(2, picos_to_mclk(2500));
+	acttoact_mclk = max(picos_to_mclk(common_dimm->trrds_ps), 4U);
+	wrtord_mclk = max(2U, picos_to_mclk(2500));
 	if ((wrrec_mclk < 1) || (wrrec_mclk > 24))
 		printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk);
 	else
@@ -627,14 +627,14 @@ static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 	wr_data_delay = popts->write_data_delay;
 #ifdef CONFIG_SYS_FSL_DDR4
 	cpo = 0;
-	cke_pls = max(3, picos_to_mclk(5000));
+	cke_pls = max(3U, picos_to_mclk(5000));
 #elif defined(CONFIG_SYS_FSL_DDR3)
 	/*
 	 * cke pulse = max(3nCK, 7.5ns) for DDR3-800
 	 *             max(3nCK, 5.625ns) for DDR3-1066, 1333
 	 *             max(3nCK, 5ns) for DDR3-1600, 1866, 2133
 	 */
-	cke_pls = max(3, picos_to_mclk(mclk_ps > 1870 ? 7500 :
+	cke_pls = max(3U, picos_to_mclk(mclk_ps > 1870 ? 7500 :
 				       (mclk_ps > 1245 ? 5625 : 5000)));
 #else
 	cke_pls = FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR;
@@ -1810,9 +1810,9 @@ static void set_timing_cfg_7(fsl_ddr_cfg_regs_t *ddr,
 	unsigned int txpr, tcksre, tcksrx;
 	unsigned int cke_rst, cksre, cksrx, par_lat, cs_to_cmd;
 
-	txpr = max(5, picos_to_mclk(common_dimm->trfc1_ps + 10000));
-	tcksre = max(5, picos_to_mclk(10000));
-	tcksrx = max(5, picos_to_mclk(10000));
+	txpr = max(5U, picos_to_mclk(common_dimm->trfc1_ps + 10000));
+	tcksre = max(5U, picos_to_mclk(10000));
+	tcksrx = max(5U, picos_to_mclk(10000));
 	par_lat = 0;
 	cs_to_cmd = 0;
 
@@ -1877,7 +1877,7 @@ static void set_timing_cfg_8(fsl_ddr_cfg_regs_t *ddr,
 	}
 
 	acttoact_bg = picos_to_mclk(common_dimm->trrdl_ps);
-	wrtord_bg = max(4, picos_to_mclk(7500));
+	wrtord_bg = max(4U, picos_to_mclk(7500));
 	if (popts->otf_burst_chop_en)
 		wrtord_bg += 2;