path: root/doc
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authorTom Rini <>2015-02-10 10:42:56 -0500
committerTom Rini <>2015-02-10 10:42:56 -0500
commitdb7a7dee6878fe7539d5967de1caff83246254e0 (patch)
tree27a94cac552d2015cc53cd29658f15f834475a5c /doc
parentc956662cc3e2475b451afa9a8b639c0ccc49d432 (diff)
parentba877efb802edb7080703e4dd99e51a437e44f26 (diff)
Merge branch 'master' of git://
Diffstat (limited to 'doc')
1 files changed, 128 insertions, 9 deletions
diff --git a/doc/README.x86 b/doc/README.x86
index 7df8cc516a..fb87682e05 100644
--- a/doc/README.x86
+++ b/doc/README.x86
@@ -18,11 +18,11 @@ U-Boot supports running as a coreboot [1] payload on x86. So far only Link
on other x86 boards since coreboot deals with most of the low-level details.
U-Boot also supports booting directly from x86 reset vector without coreboot,
-aka raw support or bare support. Currently Link and Intel Crown Bay board
-support running U-Boot 'bare metal'.
+aka raw support or bare support. Currently Link, Intel Crown Bay, Intel
+Minnowboard Max and Intel Galileo support running U-Boot 'bare metal'.
-As for loading OS, U-Boot supports directly booting a 32-bit or 64-bit Linux
-kernel as part of a FIT image. It also supports a compressed zImage.
+As for loading an OS, U-Boot supports directly booting a 32-bit or 64-bit
+Linux kernel as part of a FIT image. It also supports a compressed zImage.
Build Instructions
@@ -47,13 +47,15 @@ Change the 'Board configuration file' and 'Board Device Tree Source (dts) file'
to point to a new board. You can also change the Cache-As-RAM (CAR) related
settings here if the default values do not fit your new board.
-Building ROM version of U-Boot (hereafter referred to as u-boot.rom) is a
+Building a ROM version of U-Boot (hereafter referred to as u-boot.rom) is a
little bit tricky, as generally it requires several binary blobs which are not
shipped in the U-Boot source tree. Due to this reason, the u-boot.rom build is
not turned on by default in the U-Boot source tree. Firstly, you need turn it
-on by uncommenting the following line in the main U-Boot Makefile:
+on by enabling the ROM build:
-# ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom
+$ export BUILD_ROM=y
+This tells the Makefile to build u-boot.rom as a target.
Link-specific instructions:
@@ -108,6 +110,50 @@ Now you can build U-Boot and obtain u-boot.rom
$ make crownbay_defconfig
$ make all
+Intel Minnowboard Max instructions:
+This uses as FSP as with Crown Bay, except it is for the Atom E3800 series.
+Download this and get the .fd file (BAYTRAIL_FSP_GOLD_003_16-SEP-2014.fd at
+the time of writing). Put it in the board directory:
+Obtain the VGA RAM (Vga.dat at the time of writing) and put it into the same
+directory: board/intel/minnowmax/vga.bin
+You still need two more binary blobs. These come from the sample SPI image
+provided in the FSP (SPI.bin at the time of writing).
+Use ifdtool in the U-Boot tools directory to extract the images from that
+file, for example:
+ $ ./tools/ifdtool -x BayleyBay/SPI.bin
+ $ cp flashregion_2_intel_me.bin board/intel/minnowmax/me.bin
+ $ cp flashregion_0_flashdescriptor.bin board/intel/minnowmax/descriptor.bin
+Now you can build U-Boot and obtain u-boot.rom
+$ make minnowmax_defconfig
+$ make all
+Intel Galileo instructions:
+Only one binary blob is needed for Remote Management Unit (RMU) within Intel
+Quark SoC. Not like FSP, U-Boot does not call into the binary. The binary is
+needed by the Quark SoC itself.
+You can get the binary blob from Quark Board Support Package from Intel website:
+* ./QuarkSocPkg/QuarkNorthCluster/Binary/QuarkMicrocode/RMU.bin
+Rename the file and put it to the board directory by:
+ $ cp RMU.bin board/intel/galileo/rmu.bin
+Now you can build U-Boot and obtain u-boot.rom
+$ make galileo_defconfig
+$ make all
Test with coreboot
For testing U-Boot as the coreboot payload, there are things that need be paid
@@ -126,11 +172,21 @@ Make sure 0x1110000 matches CONFIG_SYS_TEXT_BASE and 0x1110015 matches the
symbol address of _start (in arch/x86/cpu/start.S).
If you want to use ELF as the coreboot payload, change U-Boot configuration to
+To enable video you must enable these options in coreboot:
+ - Set framebuffer graphics resolution (1280x1024 32k-color (1:5:5))
+ - Keep VESA framebuffer
+At present it seems that for Minnowboard Max, coreboot does not pass through
+the video information correctly (it always says the resolution is 0x0). This
+works correctly for link though.
CPU Microcode
-Modern CPU usually requires a special bit stream called microcode [5] to be
+Modern CPUs usually require a special bit stream called microcode [5] to be
loaded on the processor after power up in order to function properly. U-Boot
has already integrated these as hex dumps in the source tree.
@@ -162,6 +218,69 @@ mtrr - List and set the Memory Type Range Registers (MTRR). These are used to
mode to use. U-Boot sets up some reasonable values but you can
adjust then with this command.
+Development Flow
+These notes are for those who want to port U-Boot to a new x86 platform.
+Since x86 CPUs boot from SPI flash, a SPI flash emulator is a good investment.
+The Dediprog em100 can be used on Linux. The em100 tool is available here:
+On Minnowboard Max the following command line can be used:
+ sudo em100 -s -p LOW -d u-boot.rom -c W25Q64DW -r
+A suitable clip for connecting over the SPI flash chip is here:
+This allows you to override the SPI flash contents for development purposes.
+Typically you can write to the em100 in around 1200ms, considerably faster
+than programming the real flash device each time. The only important
+limitation of the em100 is that it only supports SPI bus speeds up to 20MHz.
+This means that images must be set to boot with that speed. This is an
+Intel-specific feature - e.g. tools/ifttool has an option to set the SPI
+speed in the SPI descriptor region.
+If your chip/board uses an Intel Firmware Support Package (FSP) it is fairly
+easy to fit it in. You can follow the Minnowboard Max implementation, for
+example. Hopefully you will just need to create new files similar to those
+in arch/x86/cpu/baytrail which provide Bay Trail support.
+If you are not using an FSP you have more freedom and more responsibility.
+The ivybridge support works this way, although it still uses a ROM for
+graphics and still has binary blobs containing Intel code. You should aim to
+support all important peripherals on your platform including video and storage.
+Use the device tree for configuration where possible.
+For the microcode you can create a suitable device tree file using the
+microcode tool:
+ ./tools/microcode-tool -d microcode.dat create <model>
+or if you only have header files and not the full Intel microcode.dat database:
+ ./tools/microcode-tool -H BAY_TRAIL_FSP_KIT/Microcode/M0130673322.h \
+ -H BAY_TRAIL_FSP_KIT/Microcode/M0130679901.h \
+ create all
+These are written to arch/x86/dts/microcode/ by default.
+Note that it is possible to just add the micrcode for your CPU if you know its
+model. U-Boot prints this information when it starts
+ CPU: x86_64, vendor Intel, device 30673h
+so here we can use the M0130673322 file.
+If you platform can display POST codes on two little 7-segment displays on
+the board, then you can use post_code() calls from C or assembler to monitor
+boot progress. This can be good for debugging.
+If not, you can try to get serial working as early as possible. The early
+debug serial port may be useful here. See setup_early_uart() for an example.
- Audio
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